Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[PJVol]

Could these be legit?

 

[tsamolotoff]

Could these be legit?

That's like a two weeks old 'leak' by MSI, and they've tested Wukong and SOTTR in 4K or something like that

 

[PJVol]

That's like a two weeks old 'leak' by MSI, and they've tested Wukong and SOTTR in 4K or something like that

Why in quotes?

 

[Josh128]

Got another 6% in Dawntrail. I havent tweaked my RAM much other than maxing tREFI. At this point I suspect my 6700XT is probably limiting factor.


Seems like I have one of the highest 9900X ST scores in GB also, not that there are that many to choose from. 😉

Micro-Star International Co., Ltd. MS-7E12 - Geekbench

Benchmark results for a Micro-Star International Co., Ltd. MS-7E12 with an AMD Ryzen 9 9900X processor.

browser.geekbench.com

 

[arcky]

Why in quotes?

It’s these slides from a larger presentation that hardwareluxx attended and for some reason photographed (despite nda language on the literal slides they photographed) at msi offices and then briefly published on their website before removing. There’s errors in the slides (discrepancies between titles and legends), only 3 games tested, and very little transparency into testing conditions, so make of them what you will. ‘Leak’ in the sense that they were intentionally presented by MSI to press but not intended for wider consumption.

 

[PJVol]

‘Leak’ in the sense that they were intentionally presented by MSI to press but not intended for wider consumption.

Ah... gotcha, so it was intentional... )
Anyway, whoever wrote that news, they said 9950x3d has the same l3 laylout as the 7950x3d.

 

[lopri]

sure

before (EXPO enabled, all timmings auto):

View attachment 110282

After (EXPO enabled, all timmings auto):

View attachment 110283

So as @tsamolotoff said, it sets tREFI to a higher value and tRFC to a lower value.. and thats it

btw @Hitman928, I set "EXPO/XMP high bandwidth support" to disabled, and it was not enabled after enabling this x3d turbo mode thing (and restarting) 🧐

Did you set MEM VPP at 1.35 manually or is it by the board's auto? I am seeing 1.80 when left auto. As a matter of fact I do not even remember I've seen that option in the BIOS.

 

[Joe NYC]

Hmm...

https://twitter.com/x/status/1850102165043601433

 

[Det0x]

Pretty old "news" at this point if you have been following this thread 😉

 

[Joe NYC]

Pretty old "news" at this point if you have been following this thread 😉

A lot of speculation, but this could be called a leak. 🙂

 

[Joe NYC]

Pretty old "news" at this point if you have been following this thread 😉

BTW, if it is true and L3 die is below, then why not make SRAM amount > 64 MB? There would be room for more on the die.

 

[igor_kavinski]

BTW, if it is true and L3 die is below, then why not make SRAM amount > 64 MB? There would be room for more on the die.

AMD is cheap. Don't you know? 🙂

 

[Joe NYC]

AMD is cheap. Don't you know? 🙂

If there is no issue with cooling (passing heat through), then one full die, on N7, should be cheaper than adding filler pieces.

Well, we will see how it is implemented. When is the announcement day / end of embargo anyway?

 

[Det0x]

BTW, if it is true and L3 die is below, then why not make SRAM amount > 64 MB? There would be room for more on the die.

Does it matter if they crush the competition 20% or 30% in gaming ? (and they kinda want to keep the die hight the same)
Think this is also the reason for the conservative clocks on the first SKU.. It will be up to us tinkers to push the silicon and really show what it can do 🙂

 

[inf64]

Does it matter if they crush the competition 20% or 30% in gaming ? (and they kinda want to keep the die hight the same)
Think this is also the reason for the conservative clocks on the first SKU.. It will be up to us tinkers to push the silicon and really show what it can do 🙂

I am hoping that 12 and 16C X3D will have higher clock 3D chiplet clocks. That would be incentive to some potential buyers to opt for higher core count X3D parts, especially if they will have higher OC ceiling on the 3D chiplet.

 

[coercitiv]

A lot of speculation, but this could be called a leak. 🙂

I believe @Det0x leaked it a while ago, although admittedly it was done "lasagna style". (if you remember the original leaks about 3D chips, they were also cryptic)

 

[Joe NYC]

Does it matter if they crush the competition 20% or 30% in gaming ? (and they kinda want to keep the die hight the same)

It does matter. It took very large performance delta for AMD to make inroads to datacenter (with chiplets), and it may take similar delta to make similar inroads in client markets.

As far as height, I was still thinking single layer, but instead of die area of 1/2 of CCD, using same die size for V-Cache as main CCD. Which should fit ~128 MB.

Think this is also the reason for the conservative clocks on the first SKU.. It will be up to us tinkers to push the silicon and really show what it can do 🙂

Yeah, it does seem like very conservative clock speed, if there isn't any inherent limiting factor, compared to standard Zen 5 CPUs. Maybe 9850x3d mid-way between Zen 5 and Zen 6 releases.

 

[sl0519]

https://pbs.twimg.com/media/GaLTfYuagAAeh37?format=jpg&name=large

If there's no announcement being made then what is this invitation letter for??

 

[inquiss]

It does matter. It took very large performance delta for AMD to make inroads to datacenter (with chiplets), and it may take similar delta to make similar inroads in client markets.

As far as height, I was still thinking single layer, but instead of die area of 1/2 of CCD, using same die size for V-Cache as main CCD. Which should fit ~128 MB.



Yeah, it does seem like very conservative clock speed, if there isn't any inherent limiting factor, compared to standard Zen 5 CPUs. Maybe 9850x3d mid-way between Zen 5 and Zen 6 releases.

More 3D cache isn't going to help in clone markets. It's already the biggest stick. They need to crack the volume markets in OEMs and corporate and you don't do that with a low volume part (that you can't make in high volumes). Especially by making the production even lower volume by adding two stacks.

 

[MarkPost]

Did you set MEM VPP at 1.35 manually or is it by the board's auto? I am seeing 1.80 when left auto. As a matter of fact I do not even remember I've seen that option in the BIOS.

It's a Zen Timmings misread. It seems VDDQ and VPP values are exchanged

 

[MadRat]

With X3D it seems like there is even more reason to push higher memory bandwidth than ever.

 

[inquiss]

https://pbs.twimg.com/media/GaLTfYuagAAeh37?format=jpg&name=large

If there's no announcement being made then what is this invitation letter for??

Press only event to cover the launch?

 

[inquiss]

With X3D it seems like there is even more reason to push higher memory bandwidth than ever.

I thought the cache on previous versions meant you can get away with lower bandwidth before. An understated part of the value prop for them.

I see the cache chips as a way for AMD to delay IOD improvements while keeping the crown, no?

 

[Timmah!]

Well AMD did hint that the 2 CCD V cache parts were “special” no?

What else could make them special?

High price 😂

To be fair, while i would love to see dual v-cache solution myself, its likely the only way i would consider getting 9000 seriew cpu, i dont see it happening. AMD are too cheap to do it.

 

[Timorous]

BTW, if it is true and L3 die is below, then why not make SRAM amount > 64 MB? There would be room for more on the die.

Could just be that the latency trade off required to go bigger (both physically and just through a larger storage amount) provide negligible benefits.