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Question AMD Phoenix/Zen 4 APU Speculation and Discussion

Well, that's quite fast transition from RDNA2 to RDNA3. After staying on Vega igpu for so long, that's quite a fast jump,. Just Rembrandt and Raphael for RDNA2 igpu then?
 
ryanjagtap said:
Well, that's quite fast transition from RDNA2 to RDNA3. After staying on Vega igpu for so long, that's quite a fast jump,. Just Rembrandt and Raphael for RDNA2 igpu then?
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The question is if/how much faster can they go without resorting to infinity cache or similar?
 
jpiniero said:
The question is if/how much faster can they go without resorting to infinity cache or similar?
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DDR5 will provide big one time boost ( both in bw and in indendependant channels working well for GFX type workloads ). Then there is also probability that they will go to 32MB of L3 ?

Competition is heating up in a lovely way for customers, i'm loving this new resurgent AMD that no longer has to say pennies by sticking to half decade old designs.
 
JoeRambo said:
DDR5 will provide big one time boost ( both in bw and in indendependant channels working well for GFX type workloads ). Then there is also probability that they will go to 32MB of L3 ?

Competition is heating up in a lovely way for customers, i'm loving this new resurgent AMD that no longer has to say pennies by sticking to half decade old designs.
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One way that seems too obvious to be sensible, is to have 4 memory channels. Sure, it increases the cost of motherboard PCBs. but might be cheaper than increased chip size (no IF cache) and thus cost. Laptops can use as many memory channels as needed for the price/performance segment targeted.

I must be wrong in this.
 
uzzi38 said:
Monolithic still. Right now I'm not even sure if Strix Point is chiplet. Again, as I mentioned before, treat the old rumours as being out of date.
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Well, if it is staying monolithic, the other question would be would they cut the core count like they did when going to N7 since they might be able to hit the DDR5 bandwidth limits anyway.
 
maddie said:
One way that seems too obvious to be sensible, is to have 4 memory channels. Sure, it increases the cost of motherboard PCBs. but might be cheaper than increased chip size (no IF cache) and thus cost. Laptops can use as many memory channels as needed for the price/performance segment targeted.

I must be wrong in this.
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JoeRambo said:
DDR5 will provide big one time boost ( both in bw and in indendependant channels working well for GFX type workloads ). Then there is also probability that they will go to 32MB of L3 ?
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Maybe they Increase the L3 cache and implement it in such a way that it is shared between both the CPU and the igpu? (It would still increase the die size but it would be a more moderate way than adding IF cache)
 
They would probably need to design the cache and the memory system for both the CPU and GPU sides to be compatible and to be able to utilize that cache. That would take some reworking of the existing designs used.

It's definitely a good idea in my opinion and if they can also create a design that can be supplemented with additional stacked v-cache they'll have a real winner on their hands for 1080p gaming.
 
burninatortech4 said:
Any chance of an iGPU infinity cache (distinct from L3)?
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Seems doubtful. SRAM doesn't shrink as well as logic and the monolithic APUs are already large enough without adding another large cache.

It's certainly still possible and may be something we see in later chips if they don't create a unified last-level cache for their APUs. I suspect they'll keep the die size as small as possible and rely on the extra bandwidth of DDR5 to boost performance.

Once the memory really starts to constrain the GPU performance then adding in some extra cache starts to make sense. I don't know how little they can get away with, but I believe that Navi 24 uses only 16 MB and the 6400 has the same 12 CUs as the top end Rembrandt APUs. For all we know maybe even 8 MB would be enough of a boost for an APU to be worth the added die space.
 
Mopetar said:
They would probably need to design the cache and the memory system for both the CPU and GPU sides to be compatible and to be able to utilize that cache. That would take some reworking of the existing designs used.
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That actually may have been a reason to move to RDNA3 already. Then with Phoenix both Zen 4 and RDNA3 are all new and possibly saw design happen with a view on APUs usage as well from the start unlike previous gens.
 

Video by RGT on the topic.

1536 ALUs, 6 WGPs, RDNA3, potentiality of 3 GHz clock speeds and 9.216 TFLOPs.

I previously thought this thing will top around 2060. But now, knowing its RDNA3 and how high it can clock - I think Paul might be right with the assuption. This thing will be able to compete with 3060, assuming it has any form of cache that alleviates bandwidth limitations.

Let me repeat. 1536 ALUs, 3 GHz potential clock speed, and 9.216 TFLOPs.

In an APU, that is NOT custom, and will be widely available just like 5600G.
 
Glo. said:

Video by RGT on the topic.

1536 ALUs, 6 WGPs, RDNA3, potentiality of 3 GHz clock speeds and 9.216 TFLOPs.

I previously thought this thing will top around 2060. But now, knowing its RDNA3 and how high it can clock - I think Paul might be right with the assuption. This thing will be able to compete with 3060, assuming it has any form of cache that alleviates bandwidth limitations.

Let me repeat. 1536 ALUs, 3 GHz potential clock speed, and 9.216 TFLOPs.

In an APU, that is NOT custom, and will be widely available just like 5600G.
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You know with the last video when RGT said that some sources said RDNA3 but he believed it was RDNA2, I cried a little on the inside.

Anyway, I don't know about ALU count, but I think either 4 or 6 WGPs is downright certain. If I were to guess which one it'll be, I'd probably agree with @Kepler_L2 and RGT on it being 6WGPs the same way Navi33 is essentially Navi23 with all the RDNA3 upgrades on top. And if it is, then yeah, your maths is on point. In terms of pure TFLOPs it should be able to get that high.

I think in terms of actual performance it would be lower than what that suggests mind. I think hoping for 3060 levels of performance is a bit much. Perhaps even 3050 might be (a desktop 3050 is pretty much bang on twice the performance of Rembrandt with DDR5-4800) too much. But I'm hopeful it'll land somewhere between the 6500XT and 3050 if nothing else.
 
uzzi38 said:
You know with the last video when RGT said that some sources said RDNA3 but he believed it was RDNA2, I cried a little on the inside.

Anyway, I don't know about ALU count, but I think either 4 or 6 WGPs is downright certain. If I were to guess which one it'll be, I'd probably agree with @Kepler_L2 and RGT on it being 6WGPs the same way Navi33 is essentially Navi23 with all the RDNA3 upgrades on top. And if it is, then yeah, your maths is on point. In terms of pure TFLOPs it should be able to get that high.

I think in terms of actual performance it would be lower than what that suggests mind. I think hoping for 3060 levels of performance is a bit much. Perhaps even 3050 might be (a desktop 3050 is pretty much bang on twice the performance of Rembrandt with DDR5-4800) too much. But I'm hopeful it'll land somewhere between the 6500XT and 3050 if nothing else.
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Depends on compression, cache amount and memory speed. With 32MB of cache it will stomp the 6500XT and land around 6600 I reckon for 1080p. Above that it will get bested by the dGPUs but for an APU there is nothing wrong with that.

9.2 TFlops is pretty close to PS5 tier but without the bandwidth to back it up.

I can't see AMD totally dropping the small dGPU market though. Maybe they will just use cut down N33 chips or they could use low clocked N23 for that end of the market.
 
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