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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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sl0519 said:
From reddit: 9800x3D specifications appear on german price comparison website
Click to expand...
CouncilorIrissa said:
9800X3D listed, 5.2 boost.
Recent GB6 runs also top out at 5.25.
geizhals.de

AMD Ryzen 7 9800X3D ab € 428,00 (2026) | Preisvergleich Geizhals Deutschland

✔ Preisvergleich für AMD Ryzen 7 9800X3D ✔ Bewertungen ✔ Produktinfo ⇒ Kerne: 8 (8C) • Threads: 16 • Turbotakt: 5.20GHz • Basistakt: 4.70GHz… ✔ AMD ✔ Testberichte ✔ Günstig kaufen
geizhals.de geizhals.de
Click to expand...
This *may* all be just guesswork, based on claims from various 3rd parties, not from original information. (Including the part number 100-100001084WOF.)

They chose to list the stepping as "GNR-B0" BTW.
 
StefanR5R said:
This *may* all be just guesswork, based on claims from various 3rd parties, not from original information. (Including the part number 100-100001084WOF.)

They chose to list the stepping as "GNR-B0" BTW.
Click to expand...
Yeah, it's very likely placeholder data that is being corrected as more info comes out.
 
Joe NYC said:
9800x3d delidded, no V-Cache in sight

View attachment 110431

wccftech.com

Here's Your First Look at a Delidded AMD Ryzen 7 9800X3D CPU With Next-Gen 3D V-Cache Tech

AMD's Ryzen 7 9800X3D CPU has been delidded, revealing the next-generation of 3D V-Cache technology innovations for gamers.
wccftech.com wccftech.com
Click to expand...
Rather odd that they didn’t flag this as an “exclusive”, which they usually do in the past to take credit for being the first source… but I’ll give credit where credit is due and say that they rightfully have the first leak.

But then you see idiotic statements like this and you’re reminded of their incompetence.
The most interesting thing about this new stacking design is that it opens the room for another 3D V-Cache stack to be employed over the Zen 5 CCD, so you could theoretically get two stacks. This would make for a true stacked chiplet design for the desktop segment. Going such a route will be a bit tricky since power, cost, and thermals have to be kept in mind, but there is definitely a possibility, and maybe we will see such products in the future.
Click to expand...
Now why the heck would AMD sandwich the CCD between TWO cache dies?! C’mon! If you want to have multiple cache dies, you either stack them all on top or on the bottom because of how TSVs work. JFC, WTFTech writers are given a sneak peak and they come to the silliest of conclusions. *facepalm*

Edit: Wow, I found the one sane person in the comments section, and they happen to have the same thoughts as me. Of course, stupid Hassan deflects blame by basically saying “Oh, poor me. Please don’t shoot the messenger, that’s just what my source told me!” I swear to God, these hacks don’t deserve getting exclusive leaks because more than half the time they don’t use critical thinking. It’s like that opening scene in Rush Hour where Chris Tucker’s character, who is a detective, is trying to buy weapons from a guy and gets shown C4 in the back of the guy’s car and he’s all like, “Wow, that’s beautiful, man…. What am I looking at?”

IMG_4311.jpeg
 
Last edited:
Saylick said:
Rather odd that they didn’t flag this as an “exclusive”, which they usually do in the past to take credit for being the first source… but I’ll give credit where credit is due and say that they rightfully have the first leak.

But then you see idiotic statements like this and you’re reminded of their incompetence.

Now why the heck would AMD sandwich the CCD between TWO cache dies?! C’mon! If you want to have multiple cache dies, you either stack them all on top or on the bottom because of how TSVs work. JFC, WTFTech writers are given a sneak peak and they come to the silliest of conclusions. *facepalm*

Edit: Wow, I found the one sane person in the comments section, and they happen to have the same thoughts as me. Of course, stupid Hassan deflects blame by basically saying “Oh, poor me. Please don’t shoot the messenger, that’s just what my source told me!” I swear to God, these hacks don’t deserve getting exclusive leaks because more than half the time they don’t use critical thinking. It’s like that opening scene in Rush Hour where Chris Tucker’s character, who is a detective, is trying to buy weapons from a guy and gets shown C4 in the back of the guy’s car and he’s all like, “Wow, that’s beautiful, man…. What am I looking at?”

View attachment 110432
Click to expand...

Sandwiching the CCD in between Vcache dies is theoretically possible. From a stacking perspective, there's no technical reason you couldn't do it, but you'd have to have 2 different cache chiplet designs. In Zen 3 and Zen 4, the CCD already sits beneath the Vcache chiplet, so the thermals being prohibitive of this approach is not really valid. With that said, I think this approach is unlikely, even if theoretically possible, but who knows what AMD is researching in their labs.
 
Joe NYC said:
9800x3d delidded, no V-Cache in sight

View attachment 110431

wccftech.com

Here's Your First Look at a Delidded AMD Ryzen 7 9800X3D CPU With Next-Gen 3D V-Cache Tech

AMD's Ryzen 7 9800X3D CPU has been delidded, revealing the next-generation of 3D V-Cache technology innovations for gamers.
wccftech.com wccftech.com
Click to expand...

What you see on top is the "Support silicon to match the 2D CCD height"
The 3D V-Cache is below that (Red) and the thinned CCD (blue) is at the bottom.
( The slide can be found on the previous page )

1730082001912.jpeg
 
Using the images of Frizchens Fritz:

This shows the signal / power interconnects on the AM5 Zen 5 substrate and the ball grid array of the Zen 5 CCD that goes on it.

Zen 5 - AM5 substrate & CCD.jpg

I do not know how you would put the 3D V-Cache die between those two ???

Maybe AMD engineers can do wonders?

 
The only change which seems possible is that they have flipped the 3D V-cache die so that the TSV's of the CCD now connect directly to the top metal layer of the 3D V-cache.

In this case the 3D V-cache die itself would no longer need TSV's with the result that the total TSV length is halved, reducing the resistance by a factor two.
 
Hans de Vries said:
Using the images of Frizchens Fritz:

This shows the signal / power interconnects on the AM5 Zen 5 substrate and the ball grid array of the Zen 5 CCD that goes on it.

View attachment 110435

I do not know how you would put the 3D V-Cache die between those two ???

Maybe AMD engineers can do wonders?

Click to expand...

That makes more sense rather than the TSVs to nowhere. It is interesting though that the TSVs seem to no longer have the little logic circuits next to any of them.
 
Hans de Vries said:
The only change which seems possible is that they have flipped the 3D V-cache die so that the TSV's of the CCD now connect directly to the top metal layer of the 3D V-cache.

In this case the 3D V-cache die itself would no longer need TSV's with the result that the total TSV length is halved, reducing the resistance by a factor two.
Click to expand...

Wasn’t it already face to back stacking?

1730084735425.png
 
fastandfurious6 said:
what is the point of v-cache when big part of die is igpu which is not necessary?
Click to expand...
???? Wat. The iGPU is on the IO die.

The point of V-cache is to increase the odds of an L3 cache hit, which reduces the demand on RAM. This has performance and power consumption benefits for workloads that don’t fit within the normal 32 MB of L3.
 
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