Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Mopetar]

BTW, if it is true and L3 die is below, then why not make SRAM amount > 64 MB? There would be room for more on the die.

Increase in hit time may not be worth the added capacity for most apps. There are already a lot that don't gain anything from the v-cache and increasing the latency hurts the performance for all of those.

So 5.2 max boost is pretty much confirmed. If thermal restraint was lifted, why is boost still .3 Ghz down from non V-cache model??

It may still be voltage constrained, limiting the clock speed.

Another possibility is binning/market segmentation. If you want the faster boost you'll have to shell out for a 9900X3D or a 9950X3D.

 

[Josh128]

9800X3D Blender Open Data entry. 11% faster than 9700X. OC maybe? Or maybe its due to its 120W TDP vs the original 65W TDP of 9700X. Its massively faster than 7800X3D.

Blender - Open Data

Blender Open Data is a platform to collect, display and query the results of hardware and software performance tests - provided by the public.

opendata.blender.org

 

[StefanR5R]

Roughly 5.4ns for M1 [= 12 MB shared L2$] vs 2.4ns for 7950X [= 1 MB private L2$].

Or 3.8 ns for Telum [= 32 MB private L2$¹]
But that's when neither die area nor power consumption are of immediate concern.²

________
¹) of which parts can be dynamically repurposed into shared virtual L3$ (12 ns on average) or shared virtual L4$ even (which is off-chip cache).
²) almost a square inch of 7nm Samsung silicon for an 8-core chiplet, with 200 W power budget — but this is a real and honest way to obtain a ticket to La La Land. ;-)

 

[Gideon]

It's possible that they may decouple it into an L4 cache to allow the first 32MB of L3 to have a lower latency, at the expense of a few extra cycles of RAM latency.

In client (where you can probably only afford design with modification for both mobile and desktop) I'd much rather have an SLC instead of L4.

Each layer of cache adds extra complications, more tags to keep track of, etc.

That's one of the reasons Apple and Qualcomm forego L3. Unless you can afford to make the L3 big enough (say 24GB - 32GB+) you might be better off with bigger shared L2 caches and a SLC, that also benefits the GPU, NPU ...

 

[inquiss]

In client (where you can probably only afford design with modification for both mobile and desktop) I'd much rather have an SLC instead of L4.

Each layer of cache adds extra complications, more tags to keep track of, etc.

That's one of the reasons Apple and Qualcomm forego L3. Unless you can afford to make the L3 big enough (say 24GB - 32GB+) you might be better off with bigger shared L2 caches and a SLC, that also benefits the GPU, NPU ...

That's a giant L3 you're not gonna see in a long time...

 

[igor_kavinski]

That's a giant L3 you're not gonna see in a long time...

Maybe not a L3 but it could be an L5 made up of really fast highly parallel Optane memory.

 

[inquiss]

Maybe not a L3 but it could be an L5 made up of really fast highly parallel Optane memory.

Nah

 

[Gideon]

That's a giant L3 you're not gonna see in a long time...

Yeah, that's why you're not gonna see L3 on qualcomm / apple SoCs.

At least until they are 90% mobile focused. Apple's rumored server SKUs might actually have L3 and it might trickle down to higher end desktop / M Max SKUs

 

[inquiss]

Yeah, that's why you're not gonna see L3 on qualcomm / apple SoCs.

At least until they are 90% mobile focused. Apple's rumored server SKUs might actually have L3 and it might trickle down to higher end desktop / M Max SKUs

Well, yeah that and how big or high Gigabyte size L3s would be. It's absurd.

 

[yuri69]

If Zen continues to get wider and slower, than I can see them using the reduced clockspeed targets to double the size of the L2 while keeping the same number of cycles of latency. That should help with throughput a bit.

From my layman PoV investing into increasing L2 size does not yield much in terms of general-purpose IPC. Zen 4 doubled the Zen 3's relatively small 512kB L2. Yet, it was trailing the rest of "major IPC contributors" with sub-2% IPC points. Intel went the same odd L2-growing route since Willow... 512kB -> 1.25MB -> 2MB -> 2.5/3MB.

 

[Josh128]

CopeFrameX is saying on Xitter that 9800X3D is looking strong in reviews. "Better than 8% in demanding scenarios".

Y'all dont think AMD will price this thing above $449, do you?

 

[gdansk]

CopeFrameX is saying on Xitter that 9800X3D is looking strong in reviews. "Better than 8% in demanding scenarios".

Y'all dont think AMD will price this thing above $449, do you?

It'll be $450 for a few reasons. Competition isn't one of them.

 

[gaav87]

Steve will run out of chart space for 9800x3d release i think it will look smt like this:

 

[gdansk]

Steve will run out of chart space for 9800x3d release i think it will look smt like this:

View attachment 110469

It'll be lower

 

[gaav87]

It'll be lower

You will need ultrawide screen to see this chart. Trust me bro.

 

[Timorous]

You will need ultrawide screen to see this chart. Trust me bro.

Maybe in ACC or Flight Sim.

Not so sure on average.

 

[gaav87]

Maybe in ACC or Flight Sim.

Not so sure on average.

Even 10% is close to off screen on this chart xD

 

[igor_kavinski]

Even 10% is close to off screen on this chart xD

Not an issue if you can view the chart in VR. Then just tilt your head a bit to the right and you will see the bar poking out in 3D.

 

[Gideon]

Well, yeah that and how big or high Gigabyte size L3s would be. It's absurd.

Oof yeah i wrote that without double checking. Obviously I meant 24 - 32+ MB. My bad

 

[Det0x]

9800X3D Blender Open Data entry. 11% faster than 9700X. OC maybe? Or maybe its due to its 120W TDP vs the original 65W TDP of 9700X. Its massively faster than 7800X3D.

Blender - Open Data

Blender Open Data is a platform to collect, display and query the results of hardware and software performance tests - provided by the public.

opendata.blender.org

View attachment 110463

View attachment 110464

More optimzed V/F curve
X3D have always had a better one, but it have been capped by temps and voltage limits in the past. (look at 7950X3D vs 7950X at lower PPT limits (sub 160w) and compare the efficiency)

Now that Z5X3D are unhindered by temperature and nearly all voltage limits are lifted, the new V/F curve finally get the time to shine... You will see the Z5X3D models beat vanilla Zen5 in pretty much all MT workloads @ stock PPT limits
The only remaining place where regular Zen5 wins is in the light ST workloads since the v-cache cant handle much more than 5.7ghz (when silicon pushed to the limit)

 

[CouncilorIrissa]

CopeFrameX is saying on Xitter that 9800X3D is looking strong in reviews. "Better than 8% in demanding scenarios".

Y'all dont think AMD will price this thing above $449, do you?

No. But they won't price it any lower either.

 

[SteinFG]

If it's priced higher than 450 it's getting negative reviews for sure.
7800X3D was selling in large numbers at $350 just a year or so after its launch. I think AMD can just price it at 450 and give smaller discounts later, it's better long-term.
But it's AMD, they like to miss.

 

[Joe NYC]

Y'all dont think AMD will price this thing above $449, do you?

If past is a predictor of future, AMD will price it at $499 to get all the hate in the first reviews, and then within 2 months will discount it to $449

 

[lopri]

They will price X3D's higher. X3D chips are a definition of luxury. They can lower the price of regular Zen 5 products if needed to address the rest of the market.

 

[igor_kavinski]

Even if they price them at $449, they will quickly run out of stock. Probably a lot of pissed Intel users out there who were patiently waiting for Arrow Lake, saw how bad it is at gaming and decided they will switch to AMD.