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Discussion RDNA 5 / UDNA (CDNA Next) speculation

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Is MALL gone and folded into L2? It's not listed.

That's a huge hole in the lineup between a 18GB 64CU model and the 36GB 154CU one.
 
Tuna-Fish said:
hat's a huge hole in the lineup between a 18GB 64CU model and the 36GB 154CU one.
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Yeah i think there should be AT1, because there no 256bus card.
P.S Mlid saying he have document, where 64CU target below 550$ (estimate 5080-4090 perf)
 
Kepler_L2 said:
It's real but some of the numbers like CU count are slightly wrong (maybe intentionally to find out who leaks this).
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Yeah AT0 should be 192CU and AT2 72CU.
Both only make sense with 3SA/SE.
If we plebs don't get the full fat AT0 for gaming it will be the first time since Vega20, though that was a prosumer part. I think we will depending on where NV ends up.
Not shocked to see a probable H2'27 launch, all those console parts don't tape out or validate themselves.
N3P is whatever, but considering they are going for mono compute+MID N2 would be too yield/cost sensitive. Also 512b for the flagship is absolutely necessary to match NV on memory as otherwise they have easy wins in ML et al.
SolidQ said:
i feel there would be AT1? because too big gap between 64CU and 154CU
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Nope, it is great. There is no such thing as a $1k market for dGPU, you either have your halo parts or your $500-$600 market.
AT2 is the exact part I was pushing for with RDNA4 had they used GDDR7, great config, the extra 2GB is a big deal.
NV only has that market because of lack of comp pressure, GB203 could be sold for <$700 no problem.
AT0 is a fairly modest halo compared to the moonshot halo's they could've built. Still ~600mm^2 on N3P is a lotta silicon.
Tuna-Fish said:
Is MALL gone and folded into L2? It's not listed.
Click to expand...
Now this is interesting, I think MALL outside of APUs will only be used for 3D stacked parts as only they have enough compute density to overwhelm GDDR7.
Still it appears they are increasing L2 by 4x, so the dynamics will end up somewhere between current AMD L2 and NV L2.
Potentially 2x or more bandwidth with 8x the capacity vs N48 for a moest latency hit would be good enough with 512b GDDR7 for an 8SE/192CU part.
MALL becomes necessary beyond 250CU or so.
 
branch_suggestion said:
Yeah AT0 should be 192CU and AT2 72CU.
Both only make sense with 3SA/SE.
If we plebs don't get the full fat AT0 for gaming it will be the first time since Vega20, though that was a prosumer part. I think we will depending on where NV ends up.
Not shocked to see a probable H2'27 launch, all those console parts don't tape out or validate themselves.
N3P is whatever, but considering they are going for mono compute+MID N2 would be too yield/cost sensitive. Also 512b for the flagship is absolutely necessary to match NV on memory as otherwise they have easy wins in ML et al.

Nope, it is great. There is no such thing as a $1k market for dGPU, you either have your halo parts or your $500-$600 market.
AT2 is the exact part I was pushing for with RDNA4 had they used GDDR7, great config, the extra 2GB is a big deal.
NV only has that market because of lack of comp pressure, GB203 could be sold for <$700 no problem.
AT0 is a fairly modest halo compared to the moonshot halo's they could've built. Still ~600mm^2 on N3P is a lotta silicon.

Now this is interesting, I think MALL outside of APUs will only be used for 3D stacked parts as only they have enough compute density to overwhelm GDDR7.
Still it appears they are increasing L2 by 4x, so the dynamics will end up somewhere between current AMD L2 and NV L2.
Potentially 2x or more bandwidth with 8x the capacity vs N48 for a moest latency hit would be good enough with 512b GDDR7 for an 8SE/192CU part.
MALL becomes necessary beyond 250CU or so.
Click to expand...
I think they are gargantuan SAs instead, 4 SE x 2 SA x 12 WGP for AT0 and 2 SE x 2 SA x 9 WGP for AT2
 
If we take SVP comments verbatim, this should be phase 2/3 of the comeback plan, beat NV on value in mainstream, perform well vs NV across ~90% of the market, finally after that Lisa will hopefully allow them to build the hydrogen bomb.
Kepler_L2 said:
I think they are gargantuan SEs instead, 4 SE x 2 SA x 12 WGP for AT0 and 2 SE x 2 SA x 9 WGP for AT2
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Is SE scheduling that much harder than WGP scheduling in each SE to fatten them up that much?
I though XSX was bad enough.
I much prefer 8SE/4SE unless each SE is 2x the stuff of before so the same effective throughput.
adroc_thurston said:
Oh no it's not that late.
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I sure hope not but the comments are weird unless that is just obfuscation.
Actually duh, AT0 launches first Q4'26/CES'27 with AT2 at Computex/Gamescom.
adroc_thurston said:
God they sure love changing the ratios and engine org every generation.
Click to expand...
Meanwhile NV in client is just doing mild variations of the same compute hierarchy since Pascal, just pushed further each time.
 
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gdansk said:
Oh, it may only be seen in Cocytus then. They must have their ML ducks in a row first before trying to sell gamers that sorcery.
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For example, one possible config is 256CU/4 or 8 SE which would need a little over 3Ghz to get to 200TF, give it 512b G7 and 256MB of MALL below along with Matrix cores in memory and that would be around 200b xtors using ~1k mm^2 of N2/N3 class.
That is the halo config I've been thinking about for some time, would need around 800W or so to hit those clocks I think.
 
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