Discussion RDNA 5 / UDNA (CDNA Next) speculation

[1250]

Vgpr upto 1024 for MACs?

 

[1250]

Do you think companies like AMD will make any announcements regarding HBM

 

[gdansk]

Do you think companies like AMD will make any announcements regarding HBM

Haven't they already made enough announcements regarding HBM

 

[1250]

Haven't they already made enough announcements regarding HBM

Customized for LPDDR functionality

 

[adroc_thurston]

Customized for LPDDR functionality

Yes it's a base die.
Yes it's on SF4X.
Yes it has LPDDR shoreline.
Yes AMD has tapped SF2P/X PDKs.
Any questions?

 

[1250]

Any questions?

Did co-development play such a pivotal role in sam's transition to 4nm?
(They probably don't even consider it co-development)
Those in the memory guy usually dismiss its impact, treating it like a trivial late-stage addition.
(They probably think so) I owe you

 

[Tangopiper]

Yes it's a base die.
Yes it's on SF4X.
Yes it has LPDDR shoreline.
Yes AMD has tapped SF2P/X PDKs.
Any questions?

Anything actually planned for SF2P/X?

 

[adroc_thurston]

Did co-development play such a pivotal role in sam성's transition to 4nm?

No.

Those in the memory guy usually dismiss its impact, treating it like a trivial late-stage addition.

Memory is a commodity, thus their opinions are irrelevant.

Anything actually planned for SF2P/X?

Dunno.
But they tickle the PDK.

 

[1250]

What is the estimated share of AMD's contribution to this joint development? 10%?

 

[adroc_thurston]

What is the estimated share of AMD's contribution to this joint development? 10%?

Does it matter? They say and DRAM slaves obey.

 

[1250]

Does it matter? They say and DRAM slaves obey.

yeah~ I'm just curious if AMD's IPs, such as Infinity Fabric (IF), were integrated into it.
this final-last question sorry As You Know I'm still a bit of a newbie when it comes to the details

 

[adroc_thurston]

I'm just curious if AMD's IPs, such as Infinity Fabric (IF), were integrated into it.

Obviously, that's the whole point of a custom base die.
Customer IP goes there!

 

[1250]

Obviously, that's the whole point of a custom base die.
Customer IP goes there!

Left to themselves, they’ll probably reach a point where they deny it's even 'Custom'. thanks, sir

 

[inquiss]

Obviously, that's the whole point of a custom base die.
Customer IP goes there!

What's the advantage of that vs a standard stack. Where does the benefit come from?

 

[adroc_thurston]

What's the advantage of that vs a standard stack. Where does the benefit come from?

You get to pick your base die process node, and again, you put your IP there.
Consider it a miniature version of MI400's own AID.

 

[Tangopiper]

But they tickle the PDK.

They've been tickling SF PDKs for years. It's why we keep getting rumours of Samsung-made APUs etc.

Funny that they are actually using SF4 family for this custom HBM base die but nothing about that ever reached the rumour mill lol.

I supppose there was Sonoma Valley before it got axed.

 

[1250]

I understand that CDNA 4 and 5 have the same apparent CU count, and that FP8 is four times faster than FP16. In that case, what exactly would be the right way to describe what has increased or improved?

 

[1250]

Will the specs for the MI430X be disclosed alongside the MI455X?

 

[ETI4711]

I understand that CDNA 4 and 5 have the same apparent CU count,

Why do you think that the 18000 Compute Units are CUs?


See llvm/docs/AMDGPUUsage.rst

GFX942:


GFX12


GFX125x

 

[eek2121]

lol I could be in a random meeting and anytime someone says anything that sounds close to SMT I always think of this forum and SMT4...

Then I get weird looks because i'm smiling to myself.

Same! 🤣

 

[reaperrr3]

GFX125x

View attachment 140504

Huh, so GFX125x has only 128 ALUs per WGP?
Interesting.

I guess GFX130x/131x WGPs will still have 256 ALUs though, otherwise the RDNA5 VOPD improvements would be kind of pointless, unless I'm missing something.

It's also interesting that the SEs are no longer equivalent to the "agents", like they were in previous gens.
Looks like AMD introduced another control layer above SEs. I wonder if that's more about utilization, or about flexibility.
My first thought was it might've been about chiplets, but GFX94x already had chiplets too, so I guess not.

 

[Kepler_L2]

Huh, so GFX125x has only 128 ALUs per WGP?
Interesting.

I guess GFX130x/131x WGPs will still have 256 ALUs though, otherwise the RDNA5 VOPD improvements would be kind of pointless, unless I'm missing something.

It's also interesting that the SEs are no longer equivalent to the "agents", like they were in previous gens.
Looks like AMD introduced another control layer above SEs. I wonder if that's more about utilization, or about flexibility.
My first thought was it might've been about chiplets, but GFX94x already had chiplets too, so I guess not.

No, it's 256 ALUs for most vector ops.

 

[1250]

2×4×2 profit x16 256(64)16384(4) 625?

 

[1250]

He checked and says there's no LPDDR. What should I do about this?
Tell him to check again after he actually wakes up? Or some tips

 

[jpiniero]

He checked and says there's no LPDDR. What should I do about this?
Tell him to check again after he actually wakes up?

That was a dumb "rumor" anyway.