• We’re currently investigating an issue related to the forum theme and styling that is impacting page layout and visual formatting. The problem has been identified, and we are actively working on a resolution. There is no impact to user data or functionality, this is strictly a front-end display issue. We’ll post an update once the fix has been deployed. Thanks for your patience while we get this sorted.

Question AMD Phoenix/Zen 4 APU Speculation and Discussion

Page 18 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.
DisEnchantment said:
https://twitter.com/x/status/1597416676622229504
Looks like PHX won't increase CU count after all.

But very clever concept for Zen 4c in PHX2.
SW in each core sees same amount of L3, just more cores sharing L3 in Zen 4c. Same core, same AVX512, just different clocks.
But 15W seems excessive. AIE and DSP becoming 1st class citizens.

Die sizes gonna be interesting
Click to expand...
Says 4c so you know it's -redacted-.

Profanity is not allowed in the technical forums.

Daveybrat
AT Moderator
 
Last edited by a moderator:
Not a lot of sense in adding more CUs when all of the other RDNA3 goodness and the extra memory bandwidth will give it enough of a boost.

There were several people speculating about design flaws in RDNA3 limiting clock speeds. It'll be interesting to see if those were caught and fixed before these chips went into production.

I think these will make for a tidy little budget gaming PC that mostly runs e-sport titles or other titles at 1080p medium.
 
Mopetar said:
Not a lot of sense in adding more CUs when all of the other RDNA3 goodness and the extra memory bandwidth will give it enough of a boost.

There were several people speculating about design flaws in RDNA3 limiting clock speeds. It'll be interesting to see if those were caught and fixed before these chips went into production.

I think these will make for a tidy little budget gaming PC that mostly runs e-sport titles or other titles at 1080p medium.
Click to expand...

Given that AMD still hasn't bothered to release Desktop Rembrandt yet... I think you will be waiting awhile.
 
deasd said:
How can AMD do Zen4 & Zen4C within one die since they have different density? A truck load of salt again.
Click to expand...
AMD can specify in CPU_ID 8000_0026 series
::Fn8000_0026_EAX
bit31=1 -> Asymmetrical topology (2 big + 4 small cores)
bit30=1 -> Heterogeneous cores (if the above is 0, then it is x big + x small :: x=same value)

::Fn8000_0026_EBX
Zen4 data
Bit31:28 => big core (x value) // 23:16 => high performance (high value)
Zen4c data
Bit31:28 => small core (y value) // 23:16 => low power (low value)
corestuff.jpeg

However, in prior homogeneous settings small Zen2(Oberon/Mendocino) and big Zen2(Xboxs/Renoirs) are both called Zen2. I assume the actual naming scheme in a heterogeneous setting would be High-Performance Zen4 and Energy-Efficient Zen4.

HP Config:
zen4actual.jpg

EE Config (Zen1 placeholder as it is the only Zen architecture with a single-wide(noHi/Lo) FPU):
zenplaceholder.jpg plus the above L2.

Similar Int(Reduced ROB/Opcache), Different FPU(1x3-wide versus 2x3-wide), plus other miscellaneous changes.

As accurate as possible based on Zen4 PPR:
2x 0h/Performance Zen4 cores
4x 1h/Efficiency Zen4 cores
 
Last edited:
Didn't TSMC make a presentation about being able to make process tweaks on a "per block" basis on their upcoming nodes a while back? Maybe we see that here?
 
Every single time AMD said dense cores target cloud providers. Nothing hinting at client. Until they announce it I remain sceptical. I can kneel afterwards if necessary.
 
TESKATLIPOKA said:
You are welcome.
PHX2 will have weaker IGP than Rembrandt.
2 WGPs(4CU) RDNA3 vs 6WGPs(12CU) RDNA2
Of course RDNA3 has higher PPC with likely higher clocks, but at best I think It will perform like 6600U IGP If It can clock 30% higher.
I think they should have used 3WGPs instead. This way It could be also used as a more efficient replacement for Steam deck's Aerith SoC.
Click to expand...
Not all RDNA2 Rembrandt GPU's are 12CU's. Some are 6, like in the 6600U.
So how does Little Phoenix, or PHX2 with 2 RDNA3 WGP's (4CU's) fare against that? I would presume better and still more efficient.
 
Glo. said:
L2 is 1 MB. And that will play crucial role in this version of this arch being in performance between Zen 3 and Zen 4, desktop.

Its fine.
Click to expand...
I would've liked to see 32MB of L3, for power reasons more than anything, seeing as cache size can have a tremendous impact on power efficiency. In some ways 32MB of L3 is more useful on Phoenix U than it is on various Raphael desktop SKU's.


Regardless though the L2 doubled to 1MB is going to have a bit bigger of an impact, certainly on performance, and also power efficiency most likely. Still would've been nice to see a larger L3 though.
 
Is PHX2 going to be released for mainstream laptops (yes I realize it will cost more, by mainstream I just mean same as the other Pheonix SKU's would be albeit lower cost/perf) or is this almost entirely for Steam Deck/handhelds?
 
SpudLobby said:
Is PHX2 going to be released for mainstream laptops (yes I realize it will cost more, by mainstream I just mean same as the other Pheonix SKU's would be albeit lower cost/perf) or is this almost entirely for Steam Deck/handhelds?
Click to expand...
As much as I would like to see AMD introduce Big.little already in this generation, so far there has only been one tweet by a person with next to no followers. Not even rumour mills like WCCFT have adapted this so far - so a truckload of salt is needed.
 
Tigerick said:
Here is the solution from AMD that might solve the latency issue of chiplets APU. AMD has SAM (Smart Access Memory) for a year now, aka Resizeable Bar. I don't know it will be implemented on Phoenix Point but it provides me with good thinking out of it: Can PCIe replaces integrated memory controller?

PCIe is a serial bus protocol, so it is cost effective and uses less pin counts. With each new version, the bandwidth keep on increasing: PCIe 5.0 x16 can transfer 63GB/s which is still less than dual-channel LPDDR5-6400 @ 100GB/s. PCIe 6.0 x16 which has been introduced in 2022 doubles up to 121 GB/s finally has enough bandwidth. In fact CXL 3.0 (essential PCIe for DC) has CXL.mem protocol acting like memory extension.

View attachment 71932
Click to expand...
To act as a memory controller for a single CPU, you'd only need CXLmem, which is part of the original spec, so that is perfectly plausible. But saving on pins at the cost of power, bandwidth, and latency is a bad tradeoff for mobile.

CXL memory expansion is more likely to be first employed in the datacenter to support large in-memory databases etc. that benefit from tons of capacity, but can afford some performance hit. Similar to how Optane is used today. Eventually, CXL memory pooling (part of the 3.0 spec) + switching (from the 2.0 spec) will allow enormous (10s to 100s of TB) memory pools shared by an entire rack, if not more. You'd have dedicated blades solely for DRAM shared by blades of CPUs, accelerators, NICs, etc.

On the desktop, CXL memory expansion might be handy for more memory capacity without taking the performance hit to near memory demanded by 2 DIMMs per channel, and/or you could interleave the two for even more total bandwidth. But the software side might be tricky. Anyway, probably not a discussion relevant to these kind of chips, at least for the foreseeable future.
 
Regarding these rumored specs, obviously an unknown leaker should be taken with plenty of skepticism, but this sort of split would make a lot of sense. If nothing else, it would be very beneficial for AMD to add a cost-reduced part for the mainstream market. Your typical office or home PC user wouldn't really see a benefit from 8 big cores or a class-leading GPU, but they would benefit from better battery life and lower power envelopes enabled by big.LITTLE/hybrid/whatever you want to call it, and of course the cost savings of such an arrangement. Then they still have the beefed up config for light gaming, content creation, etc. Real or not, sounds like a great set of configs.

The only part that confuses me is that neither goes below 15W. I'm not sure why PHX2 wouldn't be able to scale down to ~10W, and that would let them fit it in fanless laptops. That's a pretty significant gap in AMD's lineup right now, but they should have everything they need to fill it.
 
I hope they more dynamically bin the iGPU. Rysen 6000 only cones with the option for 6 or 8 CUs.
I want to see iGPU configs like 4,6,8,12.
 
Exist50 said:
Regarding these rumored specs, obviously an unknown leaker should be taken with plenty of skepticism, but this sort of split would make a lot of sense. If nothing else, it would be very beneficial for AMD to add a cost-reduced part for the mainstream market. Your typical office or home PC user wouldn't really see a benefit from 8 big cores or a class-leading GPU, but they would benefit from better battery life and lower power envelopes enabled by big.LITTLE/hybrid/whatever you want to call it, and of course the cost savings of such an arrangement. Then they still have the beefed up config for light gaming, content creation, etc. Real or not, sounds like a great set of configs.

The only part that confuses me is that neither goes below 15W. I'm not sure why PHX2 wouldn't be able to scale down to ~10W, and that would let them fit it in fanless laptops. That's a pretty significant gap in AMD's lineup right now, but they should have everything they need to fill it.
Click to expand...
Mendocino is the current gen part for fanless designs afaik, and that'll have it's own successor.
 
SpudLobby said:
Not all RDNA2 Rembrandt GPU's are 12CU's. Some are 6, like in the 6600U.
So how does Little Phoenix, or PHX2 with 2 RDNA3 WGP's (4CU's) fare against that? I would presume better and still more efficient.
Click to expand...
You should read what you quote, because 6600U was mentioned by me.
I also compared It to 6600U not just the full 6800U.
I also mention how 4CU PHX2 should perform comparably against 6600U If It clocks 30% higher, which is 2.5GHz.
FlameTail said:
I hope they more dynamically bin the iGPU. Rysen 6000 only cones with the option for 6 or 8 CUs.
I want to see iGPU configs like 4,6,8,12.
Click to expand...
You meant 6 and 12 CU configurations.
They won't go down to 4CUs If IGP has physically 12CUs. 6 and 12 CU is not a bad option and performance difference is ~50%, the worse thing is that full IGP option doesn't exist for 6 cores.
 
Last edited:
BorisTheBlade82 said:
As much as I would like to see AMD introduce Big.little already in this generation, so far there has only been one tweet by a person with next to no followers. Not even rumour mills like WCCFT have adapted this so far - so a truckload of salt is needed.
Click to expand...
I also wonder who he is supposed to be If Glo. said He is. Is he from some well known forum?
BtW, he wrote 8 hours ago that PHX1 ≈ RX 570.
 
Not a difficult task as TPU already gives the 680M (Rembrandt GPU) as practically equal to the RX470 (1080P).
New Architecture, new process, some more clocks, RX570 should be the bare minimum (it depends of course also on power limits).
 
Last edited:
You must log in or register to reply here.

TRENDING THREADS

Back
Top