To act as a memory controller for a single CPU, you'd only need CXLmem, which is part of the original spec, so that is perfectly plausible. But saving on pins at the cost of power, bandwidth, and latency is a bad tradeoff for mobile.
CXL memory expansion is more likely to be first employed in the datacenter to support large in-memory databases etc. that benefit from tons of capacity, but can afford some performance hit. Similar to how Optane is used today. Eventually, CXL memory pooling (part of the 3.0 spec) + switching (from the 2.0 spec) will allow enormous (10s to 100s of TB) memory pools shared by an entire rack, if not more. You'd have dedicated blades solely for DRAM shared by blades of CPUs, accelerators, NICs, etc.
On the desktop, CXL memory expansion might be handy for more memory capacity without taking the performance hit to near memory demanded by 2 DIMMs per channel, and/or you could interleave the two for even more total bandwidth. But the software side might be tricky. Anyway, probably not a discussion relevant to these kind of chips, at least for the foreseeable future.