Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7 360	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	4.8 GHz	5 GHz		4.8 GHz
L3 Cache		12 MB	6 MB	12 MB		12 MB
TDP		15 - 55 W	15 - 35 W	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5x-7467	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB	48 GB	32 GB		128 GB
Bandwidth		83 GB/s	60 GB/s	136 GB/s		120 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	2.6 GHz	2 GHz		2.5 GHz
NPU		GNA 3.0	17 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[DavidC1]

Oh right, I thought you were quoting my post, nvm.
Ye, there are some changes to the core (BPU + INT PRF bump I think?), but the largest gains are seen in cache- and memory-latency bound workloads, so the SoC guys get most of the credit, followed by improvements to core IP).

You did say ISO power. SpecFP is memory sensitive but it gains nice amounts in SpecInt and Cinebench as well. Cinebench is very not sensitive to memory. The total does amount to 5-8% which would have been much less without those core changes. For just a year difference from Arrow and Lunar it's a huge design effort.

Anyway the price increases make all this moot. On the 13 Pro the AMD version is even more expensive than Pantherlake. And official inflation number is still 2-3% lulz.

 

[regen1]

An ex-Intel CEO’s mission to build a Christian AI: ‘hasten the coming of Christ’s return’

Patrick Gelsinger, executive chairman of Gloo, has made it his mission to advance Christian principles in Silicon Valley

www.theguardian.com

https://www.aol.com/articles/intel-ceo-lip-bu-tan-134000771.html

Pat was always a crackpot CEO and directly responsible for there being no 12-core P-core only CPU soon after Alder Lake launch when it became abundantly clear that gamers hated E-cores.

270K and hopefully Nova Lake will cement LBT as a savior in Intel's history. His contributions will be magnified thanks to the ineptitude of Pat. Thanks, Pat!

Not necessarily agreeing 100% with Linus here but worth a read: https://www.realworldtech.com/forum/?threadid=225440&curpostid=225451

As for LBT, his first year had more mess and U-turns. DCAI is in worse-shape than before. All the credit for foundry initiatives/PTL/GNR he is getting now has very little to do with him. It took until Pat to stop buy-back and dividends(should've stopped dividends earlier), these are not necessarily bad tools but not good when you are far behind.

 

[regen1]

I want to say Pat had to take blame for so many things he wasn't responsible for but he is one of the reasons Intel is moving to industrial tooling for IFS also starting UC and realizing P core is meh. Though he botched the GPGPU Future for Intel.
If NVL/bLLC/PTL are good product credit goes to him more than LBT.

Yeah he gets some unnecessary blame for things his predecessors messed up. It wasn't perfect but he did a lot of good things and for results of which the stock-bros could credit his successors.

He took on when CPU and esp. Foundry was quite behind and there wasn't any serious AI entry for Intel. He got delayed stuff like SPR and way worse PVC/RTB to handle. They were still trying with software side and DevRel which has been quite bad 2025 onwards. Software-side is picking up somewhat but to what extent is unknown.

We can't know for sure but if LBT took over at Pat's time would he be willing to even invest heavily on foundry side to try to reduce gap/catch up or go Frank Yeary way: split it/abandon it?
He was already downsizing the foundry until US Gov intervention and later U-turn on 18A external customers.

 

[ultradelta]

They're pretty much exactly the same. PTL here looks a bit worse because of a worse bin (*58 vs *88), accounting for the bin difference they'd be very similar.
(this is the chart of core power, with frequency on the X axis and wattage on the Y axis. For example, at 3 GHZ the 288V needs 3.54w, and 358H needs 4.08w).

I don't know how he measured it, but Pantherlake does not have pmic and MoP, so it is normal to have some extra loss in some monitoring. It does not match the data officially provided by intel, perhaps intel used a more accurate measurement method. Cougar Cove IPC has improved, performance at the same frequency is higher.

 

[ultradelta]

Pantherlake cores have improved uarch, so it's not all process.

Both cores also have improved uarch, and not just a tick.

Tick was very minor improvements like the Radix-16 divider on Penryn and 6MB cache over 4MB. Both cores in Pantherlake have significant changes way beyond that(but not full Tock). Without it the gains would have remained at 2-4%, where it's actually about double that.

Yes, I think comparing N2P with low-end 18A-P on novalake might be more accurate.

 

[511]

Yes, I think comparing N2P with low-end 18A-P on novalake might be more accurate.

not really cause we will still have like 12MBL3 vs 18MB L3 difference

 

[ultradelta]

not really cause we will still have like 12MBL3 vs 18MB L3 difference

Novalake should all be memory-side SLC. Will it help a little?

 

[Geddagod]

View attachment 142570

This dude claimed that LNC on ARL was gonna be on Intel 3 a few years ago, lmao.

I don't know how he measured it, but Pantherlake does not have pmic and MoP, so it is normal to have some extra loss in some monitoring.

Compare the curve to ARL LNC then, it's pretty much the same

not really cause we will still have like 12MBL3 vs 18MB L3 difference

Unironically lets just bench cpu-z lol

 

[511]

This dude claimed that LNC on ARL was gonna be on Intel 3 a few years ago, lmao.

Intel can make LNC on Intel 3 but i don't think that's a good decision

He is not wrong about Crestmont vs Darkmont comparison in terms of perf/clock Darkmont is fr real more than 30% better for perf/clock

https://browser.geekbench.com/v6/cpu/compare/16340136?baseline=6371598

here is GB and remember Crestmont is at 3.8Ghz while Darkmont being at 3.5Ghz

 

[Philste]

Yes.
It also has a strict cost target (it's a very mainstream part, after all) that only works out when yields go up.

And we all know how current storage prices are. They kill every hope to sell a device at the price range WCL was made for. So WCL being MIA isn't a prove for bad 18A Yields at all. They could be 100% and WCL would still be MIA because it doesn't make sense to offer these 600$ devices at 2K $ because of storage prices.

 

[adroc_thurston]

And we all know how current storage prices are. They kill every hope to sell a device at the price range WCL was made for. So WCL being MIA isn't a prove for bad 18A Yields at all. They could be 100% and WCL would still be MIA because it doesn't make sense to offer these 600$ devices at 2K $ because of storage prices.

No, DRAM and NAND pricing are hardly a problem with WCL ramp.
In itself WCL is a solution to that problem.

 

[511]

No, DRAM and NAND pricing are hardly a problem with WCL ramp.
In itself WCL is a solution to that problem.

None gets supply like Apple for RAM and Storage

 

[adroc_thurston]

None gets supply like Apple for RAM and Storage

Uh, no, it ain't that hard.
It's just that Apple has more margin leeway as a vertically integrated device manufacturer.

 

[511]

Uh, no, it ain't that hard.
It's just that Apple has more margin leeway as a vertically integrated device manufacturer.

Apple and IDM lol

 

[DrMrLordX]

Yes.
It also has a strict cost target (it's a very mainstream part, after all) that only works out when yields go up.

I thought the 18a yield problems were primarily parametric. Or at least that was the case for Panther Lake. Defect density was supposedly not that high. On a lower-clocked part like Wildcat Lake, that shouldn't be a huge issue. Unless there's something else I'm missing here.

 

[511]

I thought the 18a yield problems were primarily parametric. Or at least that was the case for Panther Lake. Defect density was supposedly not that high. On a lower-clocked part like Wildcat Lake, that shouldn't be a huge issue. Unless there's something else I'm missing here.

you are not missing anything here 18A D0 is not the problem it's parametric also it's only 80mm2 18A die from the images available online

 

[DrMrLordX]

you are not missing anything here 18A D0 is not the problem it's parametric also it's only 80mm2 18A die from the images available online

The only issue I could see is if Intel is burning 18a capacity on other SKUs leaving few wafers available for relatively low-margin parts like Wildcat Lake.

 

[adroc_thurston]

On a lower-clocked part like Wildcat Lake, that shouldn't be a huge issue

It's not lower clocked and they still need a specific % of higher bin splits to make ASPs nice.

 

[DrMrLordX]

It's not lower clocked and they still need a specific % of higher bin splits to make ASPs nice.

Peak clockspeed should be 4.8 GHz for the P-cores on the top-end Wildcat Lake. That should be easier than the 5.1 GHz on Panther Lake

 

[poke01]

Peak clockspeed should be 4.8 GHz for the P-cores on the top-end Wildcat Lake. That should be easier than the 5.1 GHz on Panther Lake

5.1GHz Panther lake is barely sold anywhere. The best they can mass produce now is the X7 358H at 4.8GHz