adroc_thurston
Diamond Member
No, configurable I/O.
MI300 already has like 12 media cores.
Duh.
Gotta ramp the D2D bandwidth and all.
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Discussion RDNA 5 / UDNA (CDNA Next) speculation
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MI300 already has like 12 media cores.
Gotta ramp the D2D bandwidth and all.
stayfrosty
Member
Isn't a design with only 2 retscale AID's kind of small? I thought with CoWoS going 5.5x reticle they would scale bigger. The design doesn't seem that much larger than the MI355x (which also has 2x retscale AID's)
Win2012R2
Golden Member
A lot easier (and cheaper) if you have only 2 diff AIDs.
If you extract things like media engines, Infinity Fabric IO/PHY, PCIe and reduce the amount of chip-to-chip interfaces you get much more usable Die area. At the same time, energy efficiency gets improved. Especially if you compare it to a 6x Base Die configuration (Die-to-Die interconnects, increased bandwidth requirements, pJ/bit). And I don't know if AMD sticks to CoWoS or changes back to EFB like used on MI250X.
The current Base Die is 13 x 29mm according to AMD. If you go beyond 800mm2 and exctract before mentioned IP-Blocks, you might land at 1.3x more usable area. Combined with N4 instead of N6 and 6um SoIC instead of 9um SoIC the gains are quite decent.
The same applies to the Top Die. You can now increase its Die Size by 1.3x (more stuff can be kept on same chip) and N3 greatly increases transistor density.
Another benefit: You do not need two Base Die version (normal and mirrored).
If you go forward to MI400 you could extend that to 12x HBM stacks and possible 3x Base Die, I don't know. But increased usable Die area and no need for Base Die mirroring stays as benefits. It would then somehow look like Clearwater Forest from Intel. But with HBM4 and much bigger Die as additions.
And maybe as an extra:
You could more easily switch or extend your Infinity Fabric Phy with e.g. LPDDR5/6 PHY and add much more and cheaper memory capacity 😉
The current Base Die is 13 x 29mm according to AMD. If you go beyond 800mm2 and exctract before mentioned IP-Blocks, you might land at 1.3x more usable area. Combined with N4 instead of N6 and 6um SoIC instead of 9um SoIC the gains are quite decent.
The same applies to the Top Die. You can now increase its Die Size by 1.3x (more stuff can be kept on same chip) and N3 greatly increases transistor density.
Another benefit: You do not need two Base Die version (normal and mirrored).
If you go forward to MI400 you could extend that to 12x HBM stacks and possible 3x Base Die, I don't know. But increased usable Die area and no need for Base Die mirroring stays as benefits. It would then somehow look like Clearwater Forest from Intel. But with HBM4 and much bigger Die as additions.
And maybe as an extra:
You could more easily switch or extend your Infinity Fabric Phy with e.g. LPDDR5/6 PHY and add much more and cheaper memory capacity 😉
stayfrosty
Member
Agree with all you said and it absolutely makes sense for MI355x. But i'm just a bit disappointed that apparently according to the article linked in the previous page that MI400 will stay with a 2x Base Die setup. So in absolute terms the design will not be THAT much bigger than MI355x. Well, except if they start stacking compute chiplets, but I doubt that.
MI400 AID/MID are N3P
stayfrosty
Member
That's hella expensive for some PHY's and Cache. I'm guessing the compute chiplets will be N2(P) and bonded with 4.5um SoIC then?
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For the XCD I don't know the node, but some N2 variant is likely imo.
Interesting.
Even more space for "stuff"
Still, if N3P for AID and MID is true, ~800mm2 AID and let's say ~200...250mm2 for each MID ist ist still much more area than MI300X and also Blackwell. And then add the fact, that compared to Blackwell you add another +600mm2 or so N2 XCDs on each AID. This thing is HUGE.
Additionally, you can scale that design to 3x AIDs, 12x XCDs and 12x HBM-Stacks. Maybe as an MI400 refresh one year later?
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marees
Platinum Member
Is CDNA Next the same as UDNA ?
www.fool.com
We are seeing strong customer interest in the MI400 series for large-scale training and inference deployments and remain on track to launch in 2026.
The CDNA next architecture takes another major leap enabling powerful rackscale solutions that tightly integrate networking CPU and GPU capabilities at the silicon level to support Instinct solutions at data center scale. We designed CDNA next to deliver leadership AI and HPC flops while expanding our memory capacity and bandwidth advantages and supporting an open ecosystem of scale-up and scale-out networking products.
Advanced Micro Devices (AMD) Q4 2024 Earnings Call Transcript | The Motley Fool
AMD earnings call for the period ending December 31, 2024.
www.fool.com
marees
Platinum Member
Updated the thread title now...
I would suggest that UDNA is real, but simply represents a long term unified product stack strategy, rather than a more absolute single µArch per generation like nVidia has.
Think of it like RDNA and CDNA sharing the same ISA for general CU + matrix units, while each has differing layout or ratio for these, and CDNA probably remains headerless.
This way software should be far more portable between the 2 separate SKU markets, while still allowing for domain specific µArch differences.
Sort of like GCN days when the enthusiast SKU had vastly higher FP64 perf vs all lower segments, something like 1/2 rate vs 1/16th rate.
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Mi400 was on the list of N2 test production wafers leaked some time ago from TSMC, so it has to be XCD.
I am curious what will be in AID, if it needs N3P.
If by WoW stacked, you mean Wafer on Wafer stacked, has there been any leak / suggestion of that?
Because, even though it seemed the way Zen 5 + V--Cache are configured, it seemed it was that way to enable WoW stacking, in the end it seems that AMD is NOT doing WoW stacking on Zen 5.
It would be neat if Medusa Halo used stacking, to put IOD functionality on a cheaper die and then a smaller iGPU on more advanced node. It might be justified for "Halo" product, even if it doesn't trickle down to mainstream products right away.
Then, how do you get more bandwidth?
Side benefit of more channels would be mor max memory capacity, which would enable running bigger AI models locally.
I wonder if the MID serves as a base for HBM4 memory, including logic portion of HBM4.
If AMD is talking about memory being one of the differentiating factors going forward, that would be a possible approach.
I do not see HBM as part of MID (Multimedia Interface Die). HBM as close as possible to compute is the best idea, therefore attached to AID.
You can differentiate in other ways:
You can differentiate in other ways:
- HBM elevated a little (EFB?) and directly attached on AID at their edges (so no HBM signal routing through the interposer), which roughly halves pJ/bit
- Stacked SRAM / V-Cache
- HBM4 could use PIM
- MID could feature additional LPDDR5/6 channels (cheaper memory and higher total memory capacity)
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The way I would picture it is, based on some info leaked
- 2 AIDs next to each other connected with fast link, maybe hybrid bond linked silicon bridge
- XCDs stacked on top of AIDs
- MID next to each AID, maybe connected with same bridge silicon bridge (or EFB?)
- HBM4 stacks (2 or 4?) stacked on top of MIO, with the base logic die being part of MID, PIM could be part of MID / HBM combo.
This would mean AID would no longer have memory controllers talking directly to HBM, it would just have a networking interface talking to neighboring bridges.
Then, custom product could be developed with different numbers of AIDs (compute) and MIDs (memory capacity)
One sticking point is if Mi400 is expected to use HBM4. I have not seen this question addressed on either NVidia or AMD side, which is what would be the first product to use HBM4
adroc_thurston
Diamond Member
Nope!
All the fun stuff is datacenter-only.
Well the architecture looks like a pretty big change at least.
adroc_thurston
Diamond Member
They're doing a major tock every cycle now.
Maxwell PTSD basically.
poke01
Diamond Member
Is it on N3E?
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