marees
Platinum Member
current strix point socket is FP8 I believe
medusa point 1 base goes into FP8
but medusa point 1 high (with optional 12p ccd) would go into FP10 & so would medusa premium
so FP10 is new. FP8 is current
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Discussion RDNA 5 / UDNA (CDNA Next) speculation
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medusa point 1 base goes into FP8
but medusa point 1 high (with optional 12p ccd) would go into FP10 & so would medusa premium
so FP10 is new. FP8 is current
adroc_thurston
Diamond Member
MrMPFR
Senior member
TBH it looks like AMD's Conroe/Maxwell IF it's scheduling, RT and data management related changes from patents end up in final product. No idea about ML though.
Add another multiplier on top for all Work Graphs workloads.
Do they need full AT0 to compete with NVIDIA? Doubt it unless NVIDIA has another large perf/area gain up their sleeve.
If Rubin is Ampere+++ with no IPC gain (ignore ML and RT) then good luck competing against AT0. With 10% IPC gain still good luck.
Assuming 24CUs per SE, perf = AT4 x 8 x clock adjusted multiplier regardless of settings and resolution used (assuming no CPU bottleneck) due to:
- Modular decentralized WGS scheduling = no CP scaling issue.
- Local launch + logic unit idle/overload polling via push or pull requests + contained SE scheduling domain = superior SE level scaling and scheduling.
MLID's AT0 154CU vs full 188-192CU prob where NVIDIA wins, but only at higher res with very low base framerate.
NVIDIA needs to fix CP and GPC frontend issues to adress scaling issues and unless Rubin is a complete redesign that's not happening.
adroc_thurston
Diamond Member
they need something twice as large.
I doubt this AT0 ultra high end chip makes it to consumer and is likely one of those phantom designs that never make it to market. The only way it makes kind of sense is it its a compute chip rather than a gaming one with compromised gaming abilities. Big monoliths are too expensive and something chiplet based is going to run into gaming issues.
AMD is pouring all it's resources into datacenter to try to catch up to Nvidia and even Zen 6 seems a bit delayed.
Consumer graphics was always a sidenote for AMD since Lisa has taken over and actually a bit before that. With GDDR7 being as expensive and low supply as it is at the moment, it will be a very low volume launch. If I was Nvidia, I would not leave a trace of GDDR7 left for the competition, especially with RUBIN CPX and my own graphic line up needing it. And I think this is what they are doing. I think this is one of reasons why Nvidia cares about their consumer lineup even with as much data center money they are making. It allows them to manipulate the supply chain and also gives them them a better position at TSMC(they may outspend even apple this year).
With Nvidia spending as much as they are in COGS(they spend in 1 quarter what AMD spends in a year), they have likely created bottlenecks in the supply chain which as a consequence impede AMD. When 2027 goes a round, consumer graphics from AMD will be subdued like RDNA 4's launch. AMD will simply have too much going on like real availability of Zen 6, production of PS6 parts and their next instinct chip. An aggressive top to bottom line up does not make sense for consumer graphics. AMD doesn't have the resources and neither does the market.
AMD is pouring all it's resources into datacenter to try to catch up to Nvidia and even Zen 6 seems a bit delayed.
Consumer graphics was always a sidenote for AMD since Lisa has taken over and actually a bit before that. With GDDR7 being as expensive and low supply as it is at the moment, it will be a very low volume launch. If I was Nvidia, I would not leave a trace of GDDR7 left for the competition, especially with RUBIN CPX and my own graphic line up needing it. And I think this is what they are doing. I think this is one of reasons why Nvidia cares about their consumer lineup even with as much data center money they are making. It allows them to manipulate the supply chain and also gives them them a better position at TSMC(they may outspend even apple this year).
With Nvidia spending as much as they are in COGS(they spend in 1 quarter what AMD spends in a year), they have likely created bottlenecks in the supply chain which as a consequence impede AMD. When 2027 goes a round, consumer graphics from AMD will be subdued like RDNA 4's launch. AMD will simply have too much going on like real availability of Zen 6, production of PS6 parts and their next instinct chip. An aggressive top to bottom line up does not make sense for consumer graphics. AMD doesn't have the resources and neither does the market.
gdansk
Diamond Member
They do, actually.
But there's very little point shipping AT0 to gamers, they won't buy it. It doesn't have DLSS 5.5 or whatever next big thing.
And it is for gaming - but multiple sessions on "one" chip.
branch_suggestion
Senior member
It is for Xbox Cloud, it is very gaming focused just not in the dGPU sense.
Also it is still much smaller than what AMD could make, always remember they have SoIC in their back pocket.
A cutdown will be sold for obvious reasons, full die comes down to how strong GR202 is.
Z6 is perfectly on time, H2'26.
Only reason why Olympic Ridge is delayed to 2027 is if there is still too much Z5 stock.
AMD will surpass Apple at TSMC by the end of the decade also, it is what it is.
Supply chain is not as black and white as you think, the suppliers decide how much of their alloc goes where, the customer can only try to manipulate future supply so much.
AMD has the resources to do whatever they like. They've decided that gamers(tm) deserve nothing and they will like it.
All RDNA5 dGPU parts are derived from other markets which is very clever but also very lame.
Seriously? Zen 6 does not necessarily have to compete with Zen 5. It complements it.
If AMD just offers 12 core Zen 6 and 24 core Zen 6, they can leave all Zen 5 on the market and they will continue to sell (for slightly less).
It looks that way, that Apple will drop to #3 at TSMC.
I don't think AMD just wants to be "mean" to gamers. It's just that client and server GPUs are close enough conceptually, and during the AI crunch time, AMD did not have enough people with the right qualifications and had to prioritize.
Client GPU was just far behind server GPU on the list of priorities. We will see how the client division is recovering by how well design RDNA5 turns out to be.
Just a tidbit from AMD financials: the client GPU division, including both dGPU and consoles is not that far ahead of datacenter GPU currently. ~$1.2 billion - $1.5 billion range.
The datacenter GPU is about to explode, which was the incentive to prioritize datacenter. But this struggle to get traction in datacenter GPU has been going on for 3 years.
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I mean, according to AMD (and Sony?) they were already done with bits of it sometime last year - so a semi custom chip isn't impossible this year, just unlikely.
Not to mention that 2 generations (XB1X and XSX) of XB hardware being technically ahead of PS hasn't given them the sales they were almost certainly betting on.
So getting a short term gain on Sony at the cost of a new console in the middle of the AI component drought really doesn't seem like any kind of smart move.
Yeah.
Given how even 8C Zen6 should easily outperform a 9700X, there's no reason to price any Zen6 SKUs so low that it would hurt 9700X and below. 9700X and below will simply take the role of mainstream offerings below 250$, while all desktop Zen6 will likely be priced at $299+ at launch.
I think AMD will stop/phase out production of dual-CCD Zen5s rather soonish.
9900X is probably more expensive to make than single-CCD Zen6 models, despite the cheaper process node.
I think AMD's line-up, after the initial batch of Zen6 SKUs is out, will look something like this:
$999 - Ryzen 9 595X3D² (24C+VCache for both CCDs)
$749 - Ryzen 9 595X (24C)
$649 - Ryzen 9 590X (20C)
$599 - Ryzen 9 580X3D (12C+VCache)
$499 - Ryzen 7 560X3D (8C+VCache)
$399 - Ryzen 7 570X (12C)
$299 - Ryzen 5 560X (8C)
$229 - Ryzen 9700X
$179 - Ryzen 9600(X)
And a few more left-over Zen4/5 SKUs nobody cares about, probably.
Dunno if they'll bother with a vanilla 10C-SKU (and call the 12C 580X instead). Could fit in nicely at $349/359, but they usually try to focus on as few SKUs as possible at first, and upselling the higher-core-count ones.
Well yeah, adroc, MLID etc. have already said it would've been a pretty complex and expensive construct, and MLID (take it for what you will) said they also cancelled it in part because they still had trouble ironing out the last remaining issues of the chiplet approach and weren't sure how much longer it'd have taken to fix those.
Basically, the mix of time-to-market uncertainty, remaining development cost to finish development, production cost/complexity and (at that time) presumed high performance of GB202, made it look too risky to put more resources into it, while the CDNA side desperately needed those engie resources.
So they decided it wasn't worth the risk and shifted those engineering resources to RDNA5 and CDNA.
adroc_thurston
Diamond Member
Bruh pipe down
adroc_thurston
Diamond Member
AMD was perfectly capable of executing on it.
They were also perfectly capable of replacing it with something more pedestrian and still halo. Theh didn't because no one at AMD cares about competing with Nvidia in client.
MrMPFR
Senior member
Possible RDNA5+/GFX13+ Scheduling Patents:
- Work Graph Scheduler Implementation
- Hierarchical work scheduling
- Synchronization Method for Low Latency Communication for Efficient Scheduling
- Inclusion of Dedicated Accelerators in Graph Nodes
- System and method for scheduling operations in a graphics pipeline
- Local launch in workgroup processors
Feature List for Patents:
#1: Modular SE level autonomous scheduling (WGS) and dispatch (ADC) and support for "arbitrarily large GPU configurations"#2: Work Graphs centric scheduling, and self-balancing work distribution
#3: WGS to Command Processor communication for #2
#4: Fixed-function units in Work Graphs and Task Graph on steroids
#5: Flexible FF pipeline ordering, two pipeline modes, and low latency scheduler push/pull FF unit overload/idle tracking
#6: Local WGP level autonomous scheduling and dispatch, 10X faster thread launch perf, and Work Graphs centric scheduling
Note: This is a compiled list of scheduling patents previously mentioned in the thread. I found lots of esoteric cachemem efficiency related scheduling patents through WIPO but those have been excluded.
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Probably a good time to phase out Zen 4 and just leave Zen 5 on the market as low end
Probably makes more sense to sell 10C SKUs in Zen 6 and not offer 8C, leave 8C and below to Zen 5.
Seems like AMD bit of a lot more they could chew, and by the time they made the decision to cancel, it was too late to add a replacement, larger monolithic die RDNA 4.
Which in retrospect, would have been a better decision.
marees
Platinum Member
navi 45, 46, 47 (if all monolithic) wouldn't have taken more time than navi 48
I believe it was a business decision that they felt the high end market was lost due to RTX/DLSS & decide to focus on RDNA 5
adroc_thurston
Diamond Member
Nope.
Nope. They just don't care.
By a hair.
GB202 looked big and massive and building something bigger was off the cards.
I think so too. In retrospect, it looks like it was a mistake to not offer just one size bigger die, xx80 level card for $999.
Or more likely, focus on Mi400, which may end up the biggest product in AMD history.
Disabling 4 cores out of 12 seems like too much.
I think that potential 8 core and 10 core Zen 6 will perform so well that AMD has to dissuade people from buying them and to instead persuade them to go for the full 12 core.
One thing may be the 7900xt strategy. Pricing of 7900xt was so close to 7950xt that people just opted for the full 7950xt.
2 ways to achieve that:
- just don't offer 8 core Zen 6, for now
- price 10 core within $30-$50 of 12 core, say $559 10C, $599 12C that people will buy the 12C and think they got a good deal spending the extra $40
adroc_thurston
Diamond Member
You're looking too much at 'cores' and not enough at freq parametrics.
I guess the big change going forward is that V-Cache parts will no longer be the dumping ground of low binned parts, and AMD will have to find new dumping ground of low bin parts...
adroc_thurston
Diamond Member
adroc_thurston
Diamond Member
That's a 1.5 years later refresh.
How does this impact launch day z6 product binning?
9800x3d was close to the bottom bin and 9850x3d is not. That's what changed.
I don't think the clock speeds improved by 400 MHz so that 9850x3d would still be the bottom bin.
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