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Discussion RDNA 5 / UDNA (CDNA Next) speculation
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The data reuse cache patent seems to be more tailored towards CPUs.
Very interesting is claim 3:
- 4 cycles = L1-Cache (48kByte on Zen 5)
- 2 cycle = Data Re-Use Cache (maybe 16kByte?)
Halfed cache latency is very impressive!
This is realized like that:
The data re-use cache sits very close to the execution units and before the Load and Store system.
If looking at the Zen 5 core diagram, this Data Re-Use Cache must therefore sit inside the Execution Engine block or between Load/Store Units and Execution Engine.
AMD’s Ryzen 9950X: Zen 5 on Desktop
AMD’s desktop Zen 5 products, codenamed Granite Ridge, are the latest in the company’s line of high performance consumer offerings.
chipsandcheese.com
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Yeah that's an L0d for (probably) Zen7The data reuse cache patent seems to be more tailored towards CPUs.
Very interesting is claim 3:
- 4 cycles = L1-Cache (48kByte on Zen 5)
- 2 cycle = Data Re-Use Cache (maybe 16kByte?)
Halfed cache latency is very impressive!
This is realized like that:
The data re-use cache sits very close to the execution units and before the Load and Store system.
If looking at the Zen 5 core diagram, this Data Re-Use Cache must therefore sit inside to Execution Engine block or between Load/Store Units and Execution Engine.
View attachment 139237AMD’s Ryzen 9950X: Zen 5 on Desktop
AMD’s desktop Zen 5 products, codenamed Granite Ridge, are the latest in the company’s line of high performance consumer offerings.
MrMPFR
Senior member
It does mention parallel processor four times. I just assumed it would be used given all the weird design choices relating to register renaming, improved queue priority, OoO etc...
Here's the patent for how they avoid flooding that data reuse cache:
US20250217298A1 - Systems and methods for reducing cache fills - Google Patents
A method for reducing cache fills can include training a filter, by at least one processor and in response to at least one of eviction or rewrite of one or more entries of a cache, the filter indicating one or more cache loads from which the one or more entries were previously filled. The method...
patents.google.com
MrMPFR
Senior member
TBH I was more interested in the other patent:
Remote tensor cores can directly access another register file (bypassing L1 and L2) through a dedicated network. Based on the description this doesn't look like a regular register file + patent says scratchpad multiple times so it could be approaching TMEM-esque design. It even allow softmax (post processing) to tap into this network and operate on register file data directly instead of doing expensive requests through L1 and L2. Won't speculate as to how fast this interconnect could be but it says it's higher than L2 data bandwidth.
Looks like this extends the concept from the 2020 Shared L1 paper to register files. Because register files have a massive bandwidth advantage, extremely low memory latency, and more tightly coupled to execution the impact on matmul should be more significant.
Saw VGPR in PS5 Pro has 1.67TB/s. So that's 6.68TB/s per WGP. C&C's measured L0 bandwidth at 210GB/s per WGP. ~32X more BW. Even if it uses smaller and tensor-core private VGPR the bandwidth advantage will still be >10X.
If we compare shared L1 paper and this across a 9 WGP shader engine (PS6 design) with RDNA 2 cachemem (just a placeholder) that amounts to total remote core bandwidth of 1.68TB/s for L0 vs 53.44TB/s for VRF. Absolutely crazy.
Also saw this one:
This is related with the stuff I shared 1.5 months ago about mixing ML data formats (fx INT4, INT8, BF8, MXFP8, FP4 etc...).
If RDNA 5 uses this, allows softmax to operate on register data, and extends PS5 Pro's WGP takeover mode to the entire SE then that would be huge. Add DSMEM, Shared L0 and other changes and it's even more impressive.
Unfortunately that likely means FSR5 won't be able to run on RDNA 4 cards.
US12443407B2 - Accelerated processing device and method of sharing data for machine learning - Google Patents
A processing device is provided which comprises a plurality of compute units configured to process data, a plurality of arithmetic logic units, instantiated separate from the plurality of compute units, and configured to store the data at the arithmetic logic units and perform calculations using...
patents.google.com
Remote tensor cores can directly access another register file (bypassing L1 and L2) through a dedicated network. Based on the description this doesn't look like a regular register file + patent says scratchpad multiple times so it could be approaching TMEM-esque design. It even allow softmax (post processing) to tap into this network and operate on register file data directly instead of doing expensive requests through L1 and L2. Won't speculate as to how fast this interconnect could be but it says it's higher than L2 data bandwidth.
Looks like this extends the concept from the 2020 Shared L1 paper to register files. Because register files have a massive bandwidth advantage, extremely low memory latency, and more tightly coupled to execution the impact on matmul should be more significant.
Saw VGPR in PS5 Pro has 1.67TB/s. So that's 6.68TB/s per WGP. C&C's measured L0 bandwidth at 210GB/s per WGP. ~32X more BW. Even if it uses smaller and tensor-core private VGPR the bandwidth advantage will still be >10X.
If we compare shared L1 paper and this across a 9 WGP shader engine (PS6 design) with RDNA 2 cachemem (just a placeholder) that amounts to total remote core bandwidth of 1.68TB/s for L0 vs 53.44TB/s for VRF. Absolutely crazy.
Also saw this one:
US20250130794A1 - Multi-format operand circuit - Google Patents
The disclosed processing circuit can perform an operation with a first operand having a first number format and a second operand having a second number format by directly using the first operand in the first number format and the second operand in the second number format to produce an output...
patents.google.com
This is related with the stuff I shared 1.5 months ago about mixing ML data formats (fx INT4, INT8, BF8, MXFP8, FP4 etc...).
If RDNA 5 uses this, allows softmax to operate on register data, and extends PS5 Pro's WGP takeover mode to the entire SE then that would be huge. Add DSMEM, Shared L0 and other changes and it's even more impressive.
Unfortunately that likely means FSR5 won't be able to run on RDNA 4 cards.
adroc_thurston
Diamond Member
GPUs already have opreuse caches, they sit right behind operand collectors.
It might get used on GPUs. But the claims are very specific given the 2/4 cycles cache latency. GPU caches are not in that latency region. At least claims 1-9 are not applicable to GPUs. The other claims 10-20 might be used for CPUs and GPUs. But probably still more beneficial for CPUs, because the invention is primarily about latency reduction beyond and lower than the L1 cache. GPUs are much more latency tolerant, so the benefit of such an L0d is lower.
I think shared caches etc. like you mention with the other patents will yield in more performance uplifts than an L0d.
It will run. But probably slower or as a tuned down version (like the FSR4 INT8 version on PS5 Pro).
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MrMPFR
Senior member
I wouldn't be so sure. If it's very different even compared to current 50 series (due to architectural changes), it'll run horribly on RDNA4, worse than FP8 emulation, or AMD will have spend time making a separate RDNA 4 version.
Last option is very unlikely considering FSR 4.1 looks like a sizeable improvement in terms of image clarity in motion, especially for foliage. Much crisper and less ghosting in KCD2. Not the only game where this is the case. If AMD thinks this is good enough they'll abandon RDNA 4 when FSR 5 happens.
100%. If only I knew how GPGPU-sim worked. Then we could get somewhat reasonable estimates before launch.
Sounds like the register file patent is a big deal, but I'm not qualified to assess what kind of impact it could make if in RDNA 5.
Regarding price, AMD will have to charge a premium because Radeon sells less than Geforce. Lowering the price won’t help much. Gamers are trained “Geforce” and AMD knows it.
If gamers get AT0, it is likely going to be priced higher than the 5090.
…and that is an “if”. A whole lot of companies are putting projects on hold due to the memory/storage insanity.
If gamers get AT0, it is likely going to be priced higher than the 5090.
…and that is an “if”. A whole lot of companies are putting projects on hold due to the memory/storage insanity.
blackangus
Senior member
I just want to say I appreciate these posts.
StanSmith
Junior Member
The only way I would buy an RDNA 5 AT0 is if it meets or beats my RTX 5090 for the same or less money. Also, the numbers are questionable from the "leak" that Tom from Moore's Law Is Dead keeps pushing that the AT0 with 154 Compute Units and 24GB of GDDR7 VRAM on the 3nm process running at ONLY 380W will beat the 5090 and be a contender with the RTX 6090. I find that difficult to believe given the TBP and AMD not being really power efficient relative to performance. Additionally, the RTX 5090 has 170 Streaming Multiprocessors which is the equivalent to a Compute Unit, so the RTX 5090 already is above what AMD's RDNA 5 AT0 is putting out when it comes to CUs vs SMs. I know the die shrink should have an IPC boost, but it all depends on if an increase from previous generations will translate to the upcoming generation.
Regardless, there were very few RTX 5090s sold compared to less expensive models, so that likely shows that the appetite for higher end GPUs is limited. AMD may take that into consideration and hold off on a flagship GPU for the discrete GPU consumer market. AMD also likely saw how successful making a strong upper-mid range GPU like the RX 9070XT was and how well that has done when going against the increasingly expensive and rare upper-mid NVIDIA GPUs like the RTX 5070TI and RTX 5080. So, AMD may stick with targeting the mid-range and gain more ground there rather than trying to expend any capital on taking on the high-end of the GPU market just yet.
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gdansk
Diamond Member
Yeah? 64CU N48 goes alright vs a 70SM GB203 chop. Might be another Factor here that helps it? Maybe a Factor that being a node of GB202 ahead could help Maximize.
A N48 chop is usually near the top of charts for power efficiency and notably VSync efficiency while hampered by obsolescent memory that has higher pj/bit transmit (poor RTX 5050, it's the least efficient Blackwell so far).
I don't know why I decided to respond to a 1 poster. The new theme makes it harder to discern. But we can't categorize RDNA5 configurations based on RDNA4 simplficiations and MLID's bogus TBP. But don't worry, it's not shipping outside of DC. We won't have to buy Radeon.
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StanSmith
Junior Member
The node ahead could be a factor, but I still don't think it will reduce power consumption to the level of 380W to produce better overall performance over the GB202.
I just joined because I want to question Kepler_L2 who is the purveyor of propaganda that MLID is peddling. Suffice it to say, I have an axe to grind with how much misinformation seems to spew from the AMD side - it's the equivalent of the "RTX 4090-level performance for $549". I just think that the rumor mills are what has led to a lot of discontentment in gamers who get fed false hope - like FSR 4 being ported to RDNA 3 and MLID and others in the TechTuber world who get people's hopes up.
I wouldn't be opposed to buying a Radeon GPU if it actually did what they are claiming it would do and be competitive to above an RTX 5090 for less money, but these guys tend to have to do damage control when things don't turn out as they've previously stated (i.e. MLID on the 9950X3D2, and Kepler_L2 on PS6 RDNA 5 claims).
It does make me wonder if RDNA 5 AT0 is going to be exclusively for enterprise clients and data centers as you alluded to.
gdansk
Diamond Member
That's another bad assumption. It will sell for more than an RTX 5090 if they caught the customer they hunted. But not to us. There's no way you build a chip that big on the hope to sell it to DLSS enthusiasts.
StanSmith
Junior Member
You're probably right. If it is released to gamers, it would almost be legally actionable (possibly so for breach of fiduciary duty to shareholders) if AMD gave a more powerful, or even equally powerful, GPU to consumers for less money. If NVIDIA cannot maintain the enthusiast/high-end GPU consumer, then something definitely went awry at NVIDIA.
MrMPFR
Senior member
5090 like 4090 is hitting a massive scaling wall. Evident if you take TPU's averaged 4K raster native numbers and compare against game clock adjusted TFLOPS.
Vs a 5070 TI and 5080 it's -26% vs 5060 TI 16GB it's -35%. Functions like a GPU with 126 and 110.5 SMs respectively.
If they fix core scaling on RDNA 5 then game over for 5090.
adroc_thurston
Diamond Member
If they win, they charge more.
Piss easy, GB202 is dogwateringly bad.
It's the smaller NV parts that are quite good.
Makaveli
Diamond Member
True based on TPU numbers a 5090 is only like 30% faster than 4090 and most people were expecting it to be much faster.
coercitiv
Diamond Member
It's open season for press grilling:
www.pcworld.com
It does not matter they're also mentioning the flawed Steam review results or some other fallacy that may come up in the near future, the end result is the same: the press can and will erode whatever mind share Radeon may still have with consumers.
But hey, good thing AMD did not release FSR4 for RDNA3 (or even some RDNA2), it may have been poorly received by the press. /s
PC graphics cards are now nearly 100 percent Nvidia
The latest analysis of the PC graphics-card market shows AMD following Intel's plunge in market share, ceding almost the entire PC graphics market to Nvidia.
www.pcworld.com
It does not matter they're also mentioning the flawed Steam review results or some other fallacy that may come up in the near future, the end result is the same: the press can and will erode whatever mind share Radeon may still have with consumers.
But hey, good thing AMD did not release FSR4 for RDNA3 (or even some RDNA2), it may have been poorly received by the press. /s
StanSmith
Junior Member
It sure seems that AMD ties its own hands behind its back and lets NVIDIA smack them around. AMD are the Washington Generals to NVIDIA's Harlem Globetrotters.
branch_suggestion
Senior member
The sad part is AMD actually has solid double digit share in DIY desktop and sales data reflects that.It's open season for press grilling:
PC graphics cards are now nearly 100 percent Nvidia
The latest analysis of the PC graphics-card market shows AMD following Intel's plunge in market share, ceding almost the entire PC graphics market to Nvidia.
It does not matter they're also mentioning the flawed Steam review results or some other fallacy that may come up in the near future, the end result is the same: the press can and will erode whatever mind share Radeon may still have with consumers.
But hey, good thing AMD did not release FSR4 for RDNA3 (or even some RDNA2), it may have been poorly received by the press. /s
Just that NV has nearly 100% share in all other discrete markets, remember ProViz counts to JPR and NV had by far their biggest quarter ever in that segment, means they are selling plenty of GB202.
Medusa Premium/Halo are for all purposes the same as a discrete AIB but will only count to overall graphics share as a iGPU.
Steam HW study needs to be paused as it leads to all sorts of flawed perceptions.
Either do everyone quarterly/yearly, fix all submissions to the proper device (Radeon Graphics smh) or don't at all.
branch_suggestion
Senior member
Speaking of that, every Project Helix is effectively an AIB PC sale for AMD too.
The nature of what entails a capable GPU has to include big integrated devices for the overall graphics share, and there AMD and Intel are not awfully far behind NV for PC all inclusive.
The nature of what entails a capable GPU has to include big integrated devices for the overall graphics share, and there AMD and Intel are not awfully far behind NV for PC all inclusive.
StanSmith
Junior Member
While I think that Steam's HW Survey needs to be revised (a beta version of this HW self-reporting is currently available), I find it odd that neither AMD nor NVIDIA will give us hard sales numbers. I think it might be because it is hard to actually track where the GPUs ultimately land once they are sold to AIB partners. Surveys can only be so definitive. I know both sides go to the data sets that most favor their narrative. I will say that AMD did a good job with the mid-range with the 9000 Series. I wonder if they will revise their business strategy for RDNA 5 and scrap the AT0 flagship GPU for gaming to remain focused on the mid-range. I assume that would only happen if RAM demand and prices remain high.
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