Question Zen 6 Speculation Thread

[inquiss]

you're posting random people off twitter.
might as well check out my account instead.

People would if you made your account more like, I dunno 5 years ago! Too tricky to get to the biggest now which l, I know is by design. Can't be caught on the morning commute browsing...

Also since when was karlo a leaker 🙂?

Though very curious what that bad news is...anyone know?

 

[adroc_thurston]

People would if you made your account more like, I dunno 5 years ago! Too tricky to get to the biggest now which l, I know is by design. Can't be caught on the morning commute browsing...

Nothing you can't solve with Samsung Galaxy(tm) S26 Ultra.
Turn the thingy on and enjoy Hasumi massives in private (in public).

Also since when was karlo a leaker 🙂?

Everyone leaks on twitter now.

 

[1250]

Zen4 4dense
Zen5 5dense
Only 6 dense
I could be wrong, but is the 'minimum core count' for Dense cores the only thing left to figure out?

 

[511]

Zen4 4dense
Zen5 5dense
Only 6 dense
I could be wrong, but is the 'minimum core count' for Dense cores the only thing left to figure out?

There is only one 32C dense CCD the other dense part is part of Medusa Point.

 

[1250]

Apologies for the confusion. What I meant was, what do you think will be the 'minimum core count' among the SP7 SKU lineup?

 

[511]

No idea but if you ask me to guess 128C

 

[reaperrr3]

No idea but if you ask me to guess 128C

I wouldn't rule out lower core count SKUs.
Not so much for yield reasons (though it may allow them to salvage a couple more bad CCDs), but because some customers may want something like "32 cores with as much non-X3D L3 as possible".
I mean, judging by desktop X3D models, VCache does seem to have some negative effect on failure rate and longevity, so not every server customer who cares about cache-per-core may want to risk using -X models.
Plus, it's a cost adder.
So I imagine having at least 1 64C and 1 32C SKU on SP7 may be a win-win for both AMD and some niche customers.

One SKU (maybe the 32C, or even a 16/8C SKU below?) with half the L3 disabled, to salvage even dies with too much dead L3, is also a possibility I guess.

 

[Tachyonism]

There is only one 32C dense CCD the other dense part is part of Medusa Point.

I wonder if it makes sense to sell 12, 16, 24 etc dense cores only SKU to consumer. Cuz I really want one.

 

[511]

I wonder if it makes sense to sell 12, 16, 24 etc dense cores only SKU to consumer. Cuz I really want one.

well they can only fit one of those CCD in Consumer part if they could but even that i doubt it depending on where the connection is

 

[Win2012R2]

No idea but if you ask me to guess 128C

That won't be minimum, no way they'll avoid making ~64 cores, for licensing purposes there will certainly be high freq ~32-ish cores too.

I mean, judging by desktop X3D models, VCache does seem to have some negative effect on failure rate and longevity

That's due to voltage pushed way too high by consumer motherboards, they clocked it too high for vCache.

 

[basix]

Better UI for browsing Phoronix results: https://www.phoronix.com/performance/result/amd-ryzen-9950x3d2

Interesting observation from the 9950X3D2 Thread:
Many AI / Inferencing Benchmarks scale well with V-Cache (e.g. oneDNN). This might be one of the reasons, why they opted for 4MB/Core L3$ for the 32C Zen 6c Chiplet. And I assume that when you put more demanding load on the CPU cores (not only web/microservices) additional cache will help as well.

 

[511]

That won't be minimum, no way they'll avoid making ~64 cores, for licensing purposes there will certainly be high freq ~32-ish cores too.

For lower count Non Dense SKU exist for 96C and for lower count SKU you want more ST performance.

 

[branch_suggestion]

Interesting observation from the 9950X3D2 Thread:
Many AI / Inferencing Benchmarks scale well with V-Cache (e.g. oneDNN). This might be one of the reasons, why they opted for 4MB/Core L3$ for the 32C Zen 6c Chiplet. And I assume that when you put more demanding load on the CPU cores (not only web/microservices) additional cache will help as well.

And Z7 dense bumps it to 7MB/core.
There really is nothing else like it.

 

[adroc_thurston]

This might be one of the reasons, why they opted for 4MB/Core L3$ for the 32C Zen 6c Chiplet

No, it's for VM farms.

 

[1250]

I'm betting on a 160-core with 16, 20, and 24-core low bins, based on the 4×9 core(full)

 

[adroc_thurston]

I'm betting on a 160-core with 16, 20, and 24-core low bins, based on the 4×9 core(full)

The full is 4*8.

 

[1250]

It's a 4*9 mesh (4*8 cores and a service row).
32c all in all. Binned ones will go into 192c SKU and friends.

🙆‍♀️ 👌

 

[adroc_thurston]

🙆‍♀️ 👌

4*9 includes the uncore stops.

 

[Markfw]

No idea but if you ask me to guess 128C

also, those who pay licenses by core count and don't need 128 cores.

 

[Doug S]

also, those who pay licenses by core count and don't need 128 cores.

If you're running Oracle you want the most performance possible per core to minimize your total license costs. So if you can squeeze a few hundred MHz sustained frequency and have more L3 per core with a smaller config you'll come out well ahead on TCO with 4x the number of 32 core blades vs 128 core.

 

[RTX]

People would if you made your account more like, I dunno 5 years ago! Too tricky to get to the biggest now which l, I know is by design. Can't be caught on the morning commute browsing...

search function doesn't show reposts

 

[Thunder 57]

search function doesn't show repostsView attachment 142523

Telling me that is adroc without telling me that is adroc?