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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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I did not see this happening. I thought AMD had more sense. I guess they decided why not take the free money?

Joe NYC said:
I think it is more likely that people just don't like asymmetric system and are willing to pay extra $50 to avoid playing lottery with the schedule choosing the right CCD.

Or don't want the hassle doing any pinning of software to CCD.



We will see how much. $50 would be totally worth it, at $100 would start to get questionable.
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$50? That's a good one. $100 at least. Now if AMD places this at current flagship prices and we get a cut on everything else down the line that would be nice.

Win2012R2 said:
It's a nice light server CPU, now with balanced large caches, good for the age of very expensive (or not available) server CPUs and extortionate memory prices.

For consumer side, especially gaming, it's a bit too little too late - Zen6 detailed info will be out soon, better to wait it out.



Yeah, even in 4k that might be bottlenecked - if I were you I'd wait for Zen 6 tho!
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This was never meant for, nor was it ever going to be good at improving game performance. So many people just didn't want to listen though. I'm glad they left games off their slide. even they don't want to show how little it does there.
 
yuri69 said:
Isn't it better to have two large L3 pools w/o juggling between a large and small L3 pool? The homogeneity principle makes things less complex.
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It's just a bad SKU like the 3900XT.
The extra cache only solves for some scheduling problems. If you had a CCD aware scheduler, what's the advantage? All threads in the process group will stay on the same CCD either way. And who is running a scheduler that does otherwise? Even the plain old 9950X wants that for optimum performance. Windows might periodically disable it in updates but I'm pretty sure that's unintentional/incompetence.
 
gdansk said:
It's just a bad SKU like the 3900XT.
The extra cache only solves for some scheduling problems. If you had a CCD aware scheduler, what's the advantage? All threads in the process group will stay on the same CCD either way. And who is running a scheduler that does otherwise? Even the plain old 9950X wants that for optimum performance. Windows might periodically disable it in updates but I'm pretty sure that's unintentional/incompetence.
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Is this trolling?

The XT line was a classic case of marketing trying to sell +100MHz faster models. There was no hidden potential besides that linear frequency gain... Unexciting.

Yet, dual-3D CCD models give you the opportunity to run 2 threads enjoying the full L3 memory stack. That alone is a significant departure from previous generations. Which opens potential to significantly speed up fitting workloads. As you mentioned, such SKUs are free from idiotic CPU driver regressions.
 
If you want to know the "significant speed gains" to be had, go back and look at the Epyc X SKUs from a few years back. Phoronix had a great benchmark list that showed which epyc SKUs did better on each subtest. there are some tests where the X SKU did MUCH better than the normal ones, but there are also some where there was no difference or a mild regression. Most of those involved database operations and code compiling. My point with harping on why this should have been an Epyc 4XXX product is that most of those gains would be in server/workstation level tasks. This will probably make a fine CPU for a VM host that hosts less than 12 reasonably sized VMs.
 
yuri69 said:
As you mentioned, such SKUs are free from idiotic CPU driver regressions.
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No, I said the opposite. They are not. Even the 9950X (similarly """homogenous""" i.e. it isn't) was not free from CPU scheduler regression in Windows. The scheduler has to be aware, for any multi-CCD part, that interactive workloads should stay within the same CCD to avoid IF hop of death (~140ns) whenever checking a lock.

The schedulers are and so... what benefit does this offer to typical customers? You can now run two games at the same time?

The cache is very niche benefit to workloads that need much L3, have more than 16 threads, and do not synchronize across CCD boundaries often. Or as people say simply to avoid the fear of scheduling jank but alas it can still suffer from the same problem which afflicted the 9950X at launch.
 
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