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Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

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DisEnchantment

DisEnchantment

Golden Member
TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

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N7 performance is more or less understood.
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This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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511 said:
Bro actually copied from a Techinsight's article and does he know how much Intel loves their HP Libraries just cause designers doesn't use HD library in a design we can't say that IFS can't fabricate or not.
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Yeah do people actually think it’s from Jukan?

It’s more than likely a Techinsights article
 
511 said:
Intel loves their HP Libraries just cause designers doesn't use HD library in a design we can't say that IFS can't fabricate or not
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And why would not designers use them if they actually work - are they getting a bonus for less chips per wafer? 😉
 
Win2012R2 said:
And why would not designers use them if they actually work - are they getting a bonus for less chips per wafer? 😉
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ask Intel designers taller cells have higher performance albeit higher leakage shorter cells have lower performance comes with lower leakage
 
It's entirely possible that he's right about Intel struggling to manufacture chips with the HD libraries, but Occam's razor would suggest in this case that it's just Intel not knowing how to design for and/or use HD libraries to any great effect.
 
eriksp92 said:
It's entirely possible that he's right about Intel struggling to manufacture chips with the HD libraries, but Occam's razor would suggest in this case that it's just Intel not knowing how to design for and/or use HD libraries to any great effect.
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Until more players adopt IFS and produce designs on Intel foundry nodes (particularly 18A which unfortunately isn't seeing major client adoption), it'll be hard to know for sure. Maybe Intel isn't even offering HD libraries to foundry customers for 18A.
 
FWIW the Intel issue of being severely dependent on HP libraries is well known, not just for CPUs but also even in GPUs. ADL-S iGPU ? HP libraries. ARC B580 ? HP libraries.
They need to show progress there.
 
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DrMrLordX said:
Until more players adopt IFS and produce designs on Intel foundry nodes (particularly 18A which unfortunately isn't seeing major client adoption), it'll be hard to know for sure. Maybe Intel isn't even offering HD libraries to foundry customers for 18A.
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They are? Otherwise it's an incomplete offering for foundry they have two cell option in 18A
HP -> G50H180
HD -> G50H160
 
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511 said:
Lmao nope
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What's the key difference between 20A and 18A? It was external PDK ready for new customers, which it wasn't - because Intel just renamed 20A to 18A in order to keep markets happy that they've hit their "5 nodes in 4 years".
 
Win2012R2 said:
What's the key difference between 20A and 18A? It was external PDK ready for new customers, which it wasn't - because Intel just renamed 20A to 18A in order to keep markets happy that they've hit their "5 nodes in 4 years".
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Nope it would be metal layers most likely just like Intel 4 and 3 have metal layer difference they belong to same family
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511 said:
Nope it would be metal layers most likely just like Intel 4 and 3 have metal layer difference they belong to same family
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So you don't actually have any info that shows differences between 20A and 18A? I am not surprised, it's the same thing right now - most likely what 18A was meant to be will become "18AP", which is when they'll get external PDK finished.
 
Win2012R2 said:
So you don't actually have any info that shows differences between 20A and 18A? I am not surprised, it's the same thing right now - most likely what 18A was meant to be will become "18AP", which is when they'll get external PDK finished.
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Well it's confusing as hell but 20A was a minimum feature set node like Intel 4 meant for ARL low tier SKU.
18A and 18AP has difference cause apparently 18AP has mobile optimization that 18A doesn't have the design is forward compatible though.
 
511 said:
Well it's confusing as hell but 20A was a minimum feature set node like Intel 4 meant for ARL low tier SKU.
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Yeah, we are supposed to believe that 20A was doing so well that they decided to move straight to 18A which was doing real crap and clearly still isn't where they'd like it to be.

It's possible 20A was just crap too and they decided to focus on 18A, but given lack of clearly shown differences it makes more likely that 20A just got rebranded as 18A.
 
Headline is wrong, but the gist they are reporting is still a big step:

https://www.reuters.com/world/china...could-yield-50-more-chips-by-2030-2026-02-23/

This doesn't help all the other foundry steps like depo/etch that are becoming more important with nanosheet GAA FETs, but having higher wafer throughput (especially as double patterning steps become necessary) is nice.

Has anyone ever seen (not behind a high paywall) anything a wafer cost model that breaks out the contribution of various factors, in particular how much of TSMC N3 or N2 wafer cost/price is EUV scanner depreciation? Going from 600W to 1000W light source would reduce that depreciation contribution by roughly 40%. One has to assume that some variable cost goes up (esp power) but it probably reduces TSMC's cost per wafer by something like a couple thousand dollars.

Not that their customers will see any of that savings, not until the AI bubble bursts and they aren't running at 100% and a waiting list! But to the extent they are able to scale up "everything else" to take advantage of higher EUV throughput, maybe it raises their wpm somewhat which does benefit their customers.
 
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