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Discussion RDNA 5 / UDNA (CDNA Next) speculation

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adroc_thurston said:
no, they'll just get bored of suckerpunching comp in DC eventually. maybe.
Click to expand...
That is the most fun outcome, I wonder when NVs roadmap does a reactor 4 reenactment.
Rubin Ultra being a super silly longboi or proper advanced packaging with Feynman sending their packaging engineers to purgatory?
Or just juiced HBM4 having a halflife of a couple months would be even funnier.
 
matrix matrix operations (shader level ML)
compute graph compiler (model level ML)

How much are above 2 techs supported in rdna 5 / cdna 5 / cdna 6 etc.?

marees said:
DirectX Compute Graph Compiler will be available for private preview this summer, please reach out to your Windows representative if you’re interested in joining.

DX Linear Algebra will enter public preview in April, giving developers an early opportunity to experiment with these capabilities and help shape the future of ML‑assisted graphics on Windows. See the Linear Algebra spec for more detail about the feature.

Introducing DX Linear Algebra​

(Last year, Cooperative Vector demonstrated that ML can be effectively integrated directly into the graphics pipeline, particularly for scenarios where developers want fine-grained, shader level control over how ML is applied alongside traditional rendering logic.

For the first time, developers could access hardware accelerated vector–matrix operations directly from HLSL, enabling a class of neural rendering techniques that execute inline with traditional shading.)

not all workloads fit this execution model. Many common and emerging scenarios—such as denoising, temporal upscaling, and more—require matrix–matrix operations, shared data across threads, and batch-oriented execution that go beyond what vector–matrix primitives alone can efficiently express.

DirectX Linear Algebra, an expansion of DirectX’s math capabilities is designed to support both vector and matrix-based ML workloads under a single programming model. DX Linear Algebra adds first-class matrix–matrix operations while preserving the ability to author ML directly in HLSL, giving developers explicit control over math, data flow, and execution for shader level ML scenarios.


Expanding to Model Level ML with DirectX Compute Graph Compiler​

DirectX Compute Graph Compiler is a new DirectX ML compiler API designed to execute full model graphs with native class GPU performance.

While shader-level ML (DX Linear Algebra above) is powerful, many modern ML-driven graphics workloads are best expressed and optimized as full computation graphs, not as isolated operators or hand-authored kernels. These graphs capture end-to-end structure—dataflow, dependencies, and deep fusion—that are difficult or impossible to exploit at the shader level, especially when targeting the full PC ecosystem.



Shader-level ML and model-level ML now live side by side in DirectX:
  1. HLSL Linear Algebra for small, inline workloads and
  2. DirectX Compute Graph Compiler for larger models.

devblogs.microsoft.com

Evolving DirectX for the ML Era on Windows - DirectX Developer Blog

At GDC this year, we shared how machine learning is becoming foundational to real time graphics, and how DirectX is evolving to meet that shift across shader level and model level ML.
devblogs.microsoft.com devblogs.microsoft.com
Click to expand...
 
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wccftech.com

AMD's RDNA 5 Has a Clever Trick That Could Nearly Double GPU Performance in Some Workloads By Working Smarter, Not Harder

AMD is working on instruction-level optimization for upcoming RDNA 5 GPUs, enabling the firm to double GPU performance.
wccftech.com wccftech.com

Source is this

www.coelacanth-dream.com

RDNA 5 ではより多くのケースで Dual Issue が機能し、ピーク FP32 性能を出しやすくなる可能性 | Coelacanth's Dream

LLVM で現在対応が進められている AMD RDNA 5 アーキテクチャ (gfx1310) だが、最近になり Dual Issue VALU/Wave32 に関するプルリクエストが公開された。 [AMDGPU] Add VOPD to gfx13 (#182815) · llvm/llvm-project@1911488 Dual Issue VALU は RDNA 3 アーキテクチャ (GFX11) から実装された機能であり、VOPD 系命令 (V_DUAL_*) を最大 2種類を組み合わせて、X側と Y側に同時に発行することができる。...
www.coelacanth-dream.com www.coelacanth-dream.com
 
It looks like the 1250, 256 CUs(similar clock?), just like the MI355X. I'm really curious to see how it manages to reach 40PF. Hype
 
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Nice Article on FP64
www.hpcwire.com

AMD Hints At Big FP64 Increases in MI430X GPU As Ozaki Underwhelms - HPCwire

Concerns with Ozaki Scheme emulation have led AMD chip designers to conclude there’s currently no substitution for raw FP64 performance. To ensure the accuracy of traditional modeling and simulation workloads, AMD Fellow Nick Malaya tells HPCwire the company intends to keep pushing the envelope...
www.hpcwire.com www.hpcwire.com

Nicholas Malaya himself linked to the Article
https://twitter.com/x/status/2032546115938025504
 
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