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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Abwx said:
Intel deal with Dell, and also with HP, date from the Opteron 64, and even before, that long predate the FX era, Intel made all they can to keep AMD from entering the server market, HP aknowldged that they refused 200k free Opteron 64 from AMD to initiate manufacturing because of fear of Intel s coercition.
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I realize there was a lot of shady stuff going on for a long time. AMD was the first to 1ghz. AMD created the first 64bit CPU. AMD had the first native dual core CPU around 2005. The tables really started turning in favor of AMD around 2002 with Athlon XP. 32bit processors had security issues and Intel believed 64 bit CPU's was unnecessary.

My first of many AMD CPU's was the AthlonXP 1800+. I upgraded to the Barton 2500+ and then the x2 3800. I had an Abit motherboard to start and then Nforce 2, Nforce 3 and I think one Nforce4 chipset boards. Those were the best boards. I had RAID O arrays to be first loading in online games. The only people who beat me loading games were using PCI-E cards. I ran RAID O gaming drives with SSD's as well.
 
igor_kavinski said:
I think it makes sense that AMD decided that if they were gonna waste some die space on two low power cores, best not to make them almost completely useless like Intel's Meteor Lake LP cores. And I believe their strategy is always to do things that help them in future. So spending the effort to make these performant LP cores could pay itself big time if AMD incorporates these LP cores as normal E-cores along with Zen6c cores acting as P-cores in a very power efficient SKU.
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apparently "zen 6" lp cores are derived from zen 5 with a topping of zen 6

Kepler_L2 said:
Yes, though the architecture is slightly different.
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Kepler_L2 said:
What AMD says publicly and what they consider the PS5 to be internally are very different things. Upcoming CPUs with "Zen6LP" are another example where despite the name, it is considered "Zen5 with Zen6 ISA" internally.
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It's a teaser; the launch happens another time... AMD didn't even post a picture of an EPYC 8005 yet. Which is why Techpowerup went ahead and put a picture of EPYC 9005 instead (non-dense version even) into their own tweet and news post. :-)
 
Looks like desktop Gorgon Point 2 for AM5 is coming out...

VideoCardz article on AI 400 desktop

No Gorgon Point full implementation 12/24/16Cu parts announced. Can't say I'm shocked as it's already heavily bandwidth bound with high spec LPDDR5 implementations. It's going to be difficult/expensive to try to best that on desktop to get maybe 15-20% better iGPU performance.
 
A few days ago, Phoronix posted a comparison of Zen 5 classic vs. Zen 5 dense (in their server incarnations):
- AMD EPYC 9755 (128 cores, Zen 5, 500 Watt TDP)
- AMD EPYC 9745 (128 cores, Zen 5C, 400 Watt TDP)
- AMD EPYC 9745 (128 cores, Zen 5C, 320 Watt cTDP)

AMD EPYC Turin 128 Core Comparison: EPYC 9745 "Zen 5C" vs. EPYC 9755 "Zen 5"

Michael Larabel said:
When taking the geometric mean of 555 benchmarks in total, the AMD EPYC 9745 was delivering about 90% the performance of its 128 core EPYC 9755 sibling. Considering that the EPYC 9745 has just 80% the TDP rating of the EPYC 9755, that's a nice showing for the EPYC 9745 with its dense cores. When pulling back to the 320 Watt lowest cTDP, it was around 98% the performance of the 400 Watt default.
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adroc_thurston said:
It also has half the L3.
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Something that will no longer be the case with Venice Dense...

But as far as full (classic) Venice CPUs, I wonder how hard AMD will be pushing V-Cache equipped Zen 6 CPUs. AMD showed Venice-X quite prominently for some Instinct AI / HPC markets.

I wonder about general purpose servers for hyperscalers, how many will adopt Venice-X.
 
Joe NYC said:
I wonder how hard AMD will be pushing V-Cache equipped Zen 6 CPUs
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Not at all.
Normal SP7 Venice covers most of the market by itself.
Per-C licensing ghetto is addressed with SP8 F and X SKUs down the line.
Joe NYC said:
AMD showed Venice-X quite prominently for some Instinct AI / HPC markets.
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Yes it's for EDA/CFD/sims/yaddayadda. No changes since Milan-X.
Joe NYC said:
I wonder about general purpose servers for hyperscalers, how many will adopt Venice-X.
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Man you're funny.
Always projecting nerd wet dreams onto unrelated product roadmaps.
 
adroc_thurston said:
Not at all.
Normal SP7 Venice covers most of the market by itself.
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This may not be the right thread, but what is your take on Venice Dense having more than 32 cores on the die? Mike Goldsmith commented on it a few days back:

I recall MLID said that about Zen 7, but not sure about Zen 6.

https://twitter.com/x/status/2026673644773191852

adroc_thurston said:
Man you're funny.
Always projecting nerd wet dreams onto unrelated product roadmaps.
Click to expand...

You also said that there would not be any more V-Cache server CPUs, while I said they would be back, even if they skip a generation (Turin).

And not only is V-Cache back (in Venice) but really integral part of Florence Dense.
 
Joe NYC said:
This may not be the right thread, but what is your take on Venice Dense having more than 32 cores on the die? Mike Goldsmith commented on it a few days back:
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Brother the next reply there is literally me.
Why are you doing this?
Joe NYC said:
You also said that there would not be any more V-Cache server CPUs
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No?
I only ever said Turin-X was shelved in favour of MI300C.
The primary customer for -X parts is Azure HPC.
Joe NYC said:
And not only is V-Cache back (in Venice) but really integral part of Florence Dense.
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a) yes. kind of.
b) not really, no. Florence is very TBD.
 
adroc_thurston said:
Brother the next reply there is literally me.
Why are you doing this?
Click to expand...

Haha, I had it bookmarked, and my reply jumped (for me) ahead of yours...

I was kind of doubtful about it too, BTW.

adroc_thurston said:
No?
I only ever said Turin-X was shelved in favour of MI300C.
The primary customer for -X parts is Azure HPC.
Click to expand...

There was another, 2nd tier hyperscaler who standardized on Genoa-X, which to me, was a clear indication there would be future V-Cache generations.

adroc_thurston said:
a) yes. kind of.
b) not really, no. Florence is very TBD.
Click to expand...

We will see if MLID leak holds, but Florence Dense would be a 2 die solution, no single die solution for the Dense part.
 
Joe NYC said:
Haha, I had it bookmarked, and my reply jumped (for me) ahead of yours...
Click to expand...
You're free to click on my account whenever.
It'll just cost you a bit of your sanity.
Joe NYC said:
There was another, 2nd tier hyperscaler who standardized on Genoa-X, which to me, was a clear indication there would be future V-Cache generations.
Click to expand...
CloudFlare and they don't work like that.
They just pick a h/w option for each server generation.
It can be AMD, Intel, QCOM (they ran Centriq 2400), whatever.
Joe NYC said:
We will see if MLID leak holds, but Florence Dense would be a 2 die solution, no single die solution for the Dense part.
Click to expand...
Please do not consider any AMD config real until it TO's.
Florence can still very much be 2D for dense SP7.
 
Saylick said:
That’s pretty good; the 9745 delivers 88% of the performance of the 9755 at 64% of the TDP.
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Right; although to those whose servers run specific workloads, it's useful to look at specific subsets of the benchmarks. (Also always consider dataset size, not just application.)
Random example: Phoronix's Linux kernel compilation 6.15 defconfig: The 320W cTDP conf of 9745 gets 86 % of the performance of 9755 @ default TDP, at 79 % of the task energy (but considering only CPU task energy, not whole system task energy which is obviously closer).

Re L3 cache: Quite many of Phoronix's benchmarks show 9745@320W and 9745@400W performing almost the same, but 9755@500W notably better than the other two. These are the workloads in which the bigger cache of 9755 gives it an edge, most likely.
 
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